AD5258BRMZ1-R7 datasheet(15/24 Pages) AD

15 / 24 page

Data Sheet

AD5258

Rev. D | Page 15 of 24

I2C INTERFACE

Note that the wiper’s default value prior to programming the

EEPROM is midscale.

The master initiates a data transfer by establishing a start con-

dition when a high-to-low transition on the SDA line occurs

while SCL is high (see Figure 3). The next byte is the slave

address byte, which consists of the slave address (first seven bits)

followed by an R/W bit (see Table 6). When the R/W bit is high,

the master reads from the slave device. When the R/W bit is

low, the master writes to the slave device.

The slave address of the part is determined by two configurable

address pins, AD0 and AD1. The state of these two pins is regis-

tered upon power-up and decoded into a corresponding I2C

7-bit address (see Table 5). The slave address corresponding to

the transmitted address bits responds by pulling the SDA line

low during the ninth clock pulse (this is termed the slave

acknowledge bit).

At this stage, all other devices on the bus remain idle while the

selected device waits for data to be written to or read from its

serial register.

WRITING

In the write mode, the last bit (R/W) of the slave address byte is

logic low. The second byte is the instruction byte. The first three

bits of the instruction byte are the command bits (see Table 6).

The user must choose whether to write to the RDAC register or

EEPROM register or to activate the software write protect (see

Table 7 to Table 10). The final five bits are all zeros (see Table 13

and Table 14). The slave again responds by pulling the SDA line

low during the ninth clock pulse.

The final byte is the data byte MSB first. Don’t cares can be

left either high or low. In the case of the write protect mode,

data is not stored; rather, a logic high in the LSB enables write

protect. Likewise, a logic low disables write protect. The slave

again responds by pulling the SDA line low during the ninth

clock pulse.

STORING/RESTORING

In this mode, only the address and instruction bytes are nec-

essary. The last bit (R/W) of the address byte is logic low. The

first three bits of the instruction byte are the command bits

(see Table 6). The two choices are transfer data from RDAC-

to-EEPROM (store) or from EEPROM-to-RDAC (restore).

The final five bits are all zeros (see Table 13 and Table 14). In

addition, users should issue an NOP command immediately

after restoring the EEMEM setting to RDAC, thereby mini-

mizing supply current dissipation.

READING

Assuming the register of interest was not just written to, it is

necessary to write a dummy address and instruction byte. The

instruction byte will vary depending on whether the data that

is wanted is the RDAC register, EEPROM register, or tolerance

After the dummy address and instruction bytes are sent, a repeat

start is necessary. After the repeat start, another address byte is

needed, except this time the R/W bit is logic high. Following

this address byte is the readback byte containing the informa-

tion requested in the instruction byte. Read bits appear on the

negative edges of the clock. Don’t cares may be in either a high

or low state.

The tolerance register can be read back individually (see

Table 15) or consecutively (see Table 16). Refer to the Read

Modes section for detailed information on the interpretation

of the tolerance bytes.

After all data bits have been read or written, a stop condition is

established by the master. A stop condition is defined as a low-

to-high transition on the SDA line while SCL is high. In write

mode, the master pulls the SDA line high during the 10th clock

pulse to establish a stop condition (see Table 8). In read mode,

the master issues a no acknowledge for the ninth clock pulse

(that is, the SDA line remains high). The master then brings the

SDA line low before the 10th clock pulse and raises SDA high to

establish a stop condition (see Table 11).

A repeated write function provides the user with the flexibility

of updating the RDAC output multiple times after addressing

and instructing the part only once. For example, after the RDAC

has acknowledged its slave address and instruction bytes in the

write mode, the RDAC output is updated on each successive

byte until a stop condition is received. If different instructions

are needed, the write/read mode must restart with a new slave

address, instruction, and data byte. Similarly, a repeated read

function of the RDAC is also allowed.

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