MPC8306S datasheet(27/70 Pages) FREESCALE

27 / 70 page

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

Ethernet and MII Management

The following figure shows the MII management AC timing diagram.

Figure 17. MII Management Interface Timing Diagram

MDC to MDIO delay

tMDKHDX

—

MDIO to MDC setup time

tMDDVKH

8.5

—

MDIO to MDC hold time

tMDDXKH

0—

—

MDC rise time

tMDCR

—

MDC fall time

tMDHF

—

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes

management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data

hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the

valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the

latter convention is used with the appropriate letter: R (rise) or F (fall).

Table 25. MII Management AC Timing Specifications (continued)

At recommended operating conditions with OVDD is 3.3 V ± 300mV.

Parameter/Condition

Symbol1

Min

Typical

Max

Unit

Note

MDC

tMDDXKH

tMDC

tMDCH

tMDCR

tMDCF

tMDDVKH

tMDKHDX

MDIO

(Input)

(Output)

MPC8306S データシート(PDF) 27 Page - Freescale Semiconductor, Inc

MPC8306S データシート(HTML) 27 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

データシートダウンロード