AD7680 datasheet(16/28 Pages) AD

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AD7688

Rev. A | Page 16 of 28

FREQUENCY (kHz)

10000

1000

100

Figure 31. PSRR vs. Frequency

The AD7688 powers down automatically at the end of each

conversion phase and, therefore, the power scales linearly with

the sampling rate, as shown in Figure 32. This makes the part

ideal for low sampling rate (even a few Hz) and low battery-

powered applications.

SAMPLING RATE (SPS)

1000

0.1

0.001

100

1000

10000

100000

1000000

VIO

VDD

Figure 32. Operating Currents vs. Sampling Rate

SUPPLYING THE ADC FROM THE REFERENCE

For simplified applications, the AD7688, with its low operating

current, can be supplied directly using the reference circuit

shown in Figure 33. The reference line can be driven by either:

•

The system power supply directly.

•

A reference voltage with enough current output capability,

such as the ADR43x.

•

A reference buffer, such as the AD8031, which can also

filter the system power supply, as shown in Figure 33.

AD8031

AD7688

VIO

REF

VDD

μF

10k

μF

1OPTIONAL REFERENCE BUFFER AND FILTER.

Figure 33. Example of Application Circuit

DIGITAL INTERFACE

Though the AD7688 has a reduced number of pins, it offers

flexibility in its serial interface modes.

The AD7688, when in CS mode, is compatible with SPI, QSPI,

digital hosts, and DSPs, e.g., Blackfin® ADSP-BF53x or ADSP-

219x. This interface can use either 3-wire or 4-wire. A 3-wire

interface using the CNV, SCK, and SDO signals minimizes

wiring connections useful, for instance, in isolated applications.

A 4-wire interface using the SDI, CNV, SCK, and SDO signals

allows CNV, which initiates the conversions, to be independent

of the readback timing (SDI). This is useful in low jitter

sampling or simultaneous sampling applications.

The AD7688, when in chain mode, provides a daisy chain

feature using the SDI input for cascading multiple ADCs on a

single data line similar to a shift register.

The mode in which the part operates depends on the SDI level

when the CNV rising edge occurs. The CS mode is selected if

SDI is high and the chain mode is selected if SDI is low. The

SDI hold time is such that when SDI and CNV are connected

together, the chain mode is always selected.

In either mode, the AD7688 offers the flexibility to optionally

force a start bit in front of the data bits. This start bit can be

used as a BUSY signal indicator to interrupt the digital host and

trigger the data reading. Otherwise, without a BUSY indicator,

the user must time out the maximum conversion time prior to

readback.

The BUSY indicator feature is enabled as:

• In the CS mode, if CNV or SDI is low when the ADC

conversion ends (

and

Figure 37

Figure 41

• In the chain mode, if SCK is high during the CNV rising edge

(Figure 45).

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