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データシートサーチシステム |
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データシートサーチシステム |
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AX250 データシート(PDF) 53 Page - Microsemi Corporation |
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AX250 データシート(HTML) 53 Page - Microsemi Corporation |
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53 / 262 page  Axcelerator Family FPGAs Re vi s i on 18 2 - 39 Timing Characteristics Table 2-32 • 1.5V LVCMOS I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 1.4 V, TJ = 70°C –2 Speed –1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS15 (JESD8-11) I/O Module Timing tDP Input Buffer 3.59 4.09 4.81 ns tPY Output Buffer 6.05 6.89 8.10 ns tENZL Enable to Pad Delay through the Output Buffer—Z to Low 3.31 3.34 3.34 ns tENZH Enable to Pad Delay through the Output Buffer—Z to High 4.56 4.58 4.59 ns tENLZ Enable to Pad Delay through the Output Buffer—Low to Z 6.37 7.25 8.52 ns tENHZ Enable to Pad Delay through the Output Buffer—High to Z 6.94 7.90 9.29 ns tIOCLKQ Sequential Clock-to-Q for the I/O Input Register 0.67 0.77 0.90 ns tIOCLKY Clock-to-output Y for the I/O Output Register and the I/O Enable Register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns |
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