AX250 datasheet(89/262 Pages) MICROSEMI

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Axcelerator Family FPGAs

Re vi s i on 18

2 - 75

Axcelerator Clock Management System

Introduction

Each member of the Axcelerator family6 contains eight phase-locked loop (PLL) blocks which perform

the following functions:

•

Programmable Delay (32 steps of 250 ps)

•

Clock Skew Minimization

•

Clock Frequency Synthesis

Each PLL has the following key features:

•

Input Frequency Range – 14 to 200 MHz

•

Output Frequency Range – 20 MHz to 1 GHz

•

Output Duty Cycle Range – 45% to 55%

•

Maximum Long-Term Jitter – 1% or 100ps (whichever is greater)

•

Maximum Short-Term Jitter – 50ps + 1% of Output Frequency

•

Maximum Acquisition Time (lock) – 20µs

Physical Implementation

The eight PLL blocks are arranged in two groups of four. One group is located in the center of the

northern edge of the chip, while the second group is centered on the southern edge. The northern group

is associated with the four HCLK networks (e.g. PLLA can drive HCLKA), while the southern group is

associated with the four CLK networks (e.g. PLLE can drive CLKE).

Each PLL cell is connected to two I/O pads and a PLL Cluster that interfaces with the FPGA core.

Figure 2-48 illustrates a PLL block. The VCCPLL pin should be connected to a 1.5V power supply

through a 250

Ω resistor. Furthermore, 0.1 μF and 10 μF decoupling capacitors should be connected

across the VCCPLL and VCOMPPLL pins.

Note: The VCOMPPLL pin should never be grounded (Figure 2-2 on page 2-9)!

The I/O pads associated with the PLL can also be configured for regular I/O functions except when it is

used as a clock buffer. The I/O pads can be configured in all the modes available to the regular I/O pads

in the same I/O bank. In particular, the [H]CLKxP pad can be configured as a differential pair,

AX2000-CQ256 does not support operation of the phase-locked loops. This is in order to support full pin compatibility with

RTAX2000S/SL-CQ256.

Figure 2-48 • PLL Block Diagram

RefCLK

Lock

DIVJ

CLK1

CLK2

FBMuxSel

DelayLine

DIVJ

LowFreq

Osc

Delay Line

PowerDown

Delay Line

PLL

/i Delay

Match

/j Delay

Match

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