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データシートサーチシステム |
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データシートサーチシステム |
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AX250 データシート(PDF) 81 Page - Microsemi Corporation |
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AX250 データシート(HTML) 81 Page - Microsemi Corporation |
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81 / 262 page  Axcelerator Family FPGAs Re vi s i on 18 2 - 67 Table 2-72 • AX500 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C –2 Speed –1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. Units Dedicated (Hardwired) Array Clock Networks tHCKL Input Low to High 2.35 2.68 3.15 ns tHCKH Input High to Low 2.44 2.79 3.27 ns tHPWH Minimum Pulse Width High 0.58 0.65 0.77 ns tHPWL Minimum Pulse Width Low 0.52 0.59 0.69 ns tHCKSW Maximum Skew 0.06 0.07 0.08 ns tHP Minimum Period 1.15 1.31 1.54 ns tHMAX Maximum Frequency 870 763 649 MHz Table 2-73 • AX1000 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C –2 Speed –1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. Units Dedicated (Hardwired) Array Clock Networks tHCKL Input Low to High 3.02 3.44 4.05 ns tHCKH Input High to Low 3.03 3.46 4.06 ns tHPWH Minimum Pulse Width High 0.58 0.65 0.77 ns tHPWL Minimum Pulse Width Low 0.52 0.59 0.69 ns tHCKSW Maximum Skew 0.06 0.07 0.08 ns tHP Minimum Period 1.15 1.31 1.54 ns tHMAX Maximum Frequency 870 763 649 MHz Table 2-74 • AX2000 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C –2 Speed –1 Speed Std Speed Parameter Description Min.Max.Min.Max.Min.Max. Units Dedicated (Hardwired) Array Clock Networks tHCKL Input Low to High 3.02 3.44 4.05 ns tHCKH Input High to Low 3.03 3.46 4.06 ns tHPWH Minimum Pulse Width High 0.58 0.65 0.77 ns tHPWL Minimum Pulse Width Low 0.52 0.59 0.69 ns tHCKSW Maximum Skew 0.06 0.07 0.08 ns tHP Minimum Period 1.15 1.31 1.54 ns tHMAX Maximum Frequency 870 763 649 MHz |
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