データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

L6717 データシート(PDF) 19 Page - STMicroelectronics

部品番号 L6717
部品情報  High-efficiency hybrid AM2r2 controller with I2C interface and embedded drivers
PDF  56 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L6717 データシート(HTML) 19 Page - STMicroelectronics

Back Button L6717 Datasheet HTML 15Page - STMicroelectronics L6717 Datasheet HTML 16Page - STMicroelectronics L6717 Datasheet HTML 17Page - STMicroelectronics L6717 Datasheet HTML 18Page - STMicroelectronics L6717 Datasheet HTML 19Page - STMicroelectronics L6717 Datasheet HTML 20Page - STMicroelectronics L6717 Datasheet HTML 21Page - STMicroelectronics L6717 Datasheet HTML 22Page - STMicroelectronics L6717 Datasheet HTML 23Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 19 / 56 page
background image
L6717
Hybrid CPU support and CPU_TYPE detection
Doc ID 17326 Rev 1
19/56
5
Hybrid CPU support and CPU_TYPE detection
L6717 is able to detect the type of the CPU-core connected and to configure itself
accordingly. At system Start-up, on the rising-edge of the EN signal, the device monitors the
status of VID1 and configures the PVI mode (VID1 = 1) or SVI mode (VID1 = 0).
When in PVI mode, L6717 uses the information available on the VID[0: 5] bus to address the
CORE Section output voltage according to Table 6. NB Section is kept in HiZ mode, both
MOSFETs are kept OFF.
When in SVI mode, L6717 ignores the information available on VID0, VID4 and VID5 and
uses VID2 and VID3 as a SVI bus addressing the CORE and NB Sections according to the
SVI protocol.
Caution:
To avoid any risk of errors in CPU type detection (i.e. detecting SVI CPU when PVI CPU is
installed on the socket and vice versa), it is recommended to carefully control the start-up
sequencing of the system hosting L6717 in order to ensure than on the EN rising-edge,
VID1 is in valid and correct state. Typical connections consider VID1 connected to CPU
CORE_TYPE through a resistor to correctly address the CPU detection.
5.1
PVI - parallel interface
PVI is a 6-bit-wide parallel interface used to address the CORE section reference. According
to the selected code, the device sets the CORE section reference and regulates its output
voltage as reported into Table 6.
NB section is always kept in HiZ; no activity is performed on this section and both the high-
side and low-side of this section are kept OFF. Furthermore, PWROK information is ignored
as well since the signal only applies to the SVI protocol.
5.2
PVI start-up
Once the PVI mode has been detected, the device uses the whole code available on the
VID[0:5] lines to define the reference for the CORE section. NB section is kept in HiZ. Soft-
start to the programmed reference is performed regardless of the state of PWROK.
See Section 7.8 for details about soft-start.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com