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L6717

Power manager I2C

Doc ID 17326 Rev 1

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6.1.1

Overspeeding command (OVRSPD)

This command allows to add a variable positive/negative offset to the CORE and/or NB

reference programmed by the SVI bus in order to overspeed the CPU. L6717 allows adding

up to 1.550 V in 50 mV steps to the reference.

The maximum possible output voltage for CORE section is internally limited to 2.8 V. In case

the SVI programmed reference plus the offset set through the OVRSPD command exceed

this value, the reference for the regulation is clamped to 2.8 V.

The maximum possible output voltage for NB section is internally limited by the maximum

offset achievable for NB section that is +600 mV over the SVI programmed reference.

Once the controller acknowledges the command and recognizes the OVRSPD command,

the reference will step up or down until reaching the target offset performing a on-the-fly VID

transition. In case a new overspeed command is issued while the output voltage is not yet

stabilized (i.e. the reference is still stepping to the target), the target is updated according to

the new offset defined.

The command addresses both sections through two separate bits in the command code

(“CN” bits - See Table 12). By asserting the corresponding bit, the subsequent data stream

will apply to the identified section. Asserting both bits (“CN” = 11b) will address both

sections. CN = 00b will be ignored regardless of the data Stream provided. “CN” = 10b and

“CN” = 01b allow to address only CORE or only NB section respectively.

010

[1:4] xxxx

[5:6] kDRPNB

[7:8] kDRP

DRP_ADJ: Droop function adjustment. Modifies the slope of the

output voltage implemented through the droop function.

[1:4]: ignored

[5:6]: kDRPNB. Defines the kDRP factor for NB section.

[7:8]: kDRP. Defines the kDRPNB factor for CORE section.

Default value is kDRPx = 1/4 for both sections.

See Table 16 for details about DRP_ADJ codification and Section 7.3

and Section 7.6 for LoadLine definition.

011

[1:3] xxx

[4:5] DPMTH

[6] PSI_A

[7] PSI_EN

[8] DPM_ON

Power management flags: Set of three flags to define power

management actions of the controller.

[1:3]: ignored

[4:5]: DPM thresholds. Default is 00b.

[6] PSI_A: PSI action. It defines the action to take when PSI_L flag is

asserted by SVI bus. The same action is considered by DPM. Send

0b to work in single phase (default) or 1b to work at two phases.

[7] PSI_EN: PSI enable. It enables or disables the PSI management.

Set to 1b (default) to manage PSI_L according to PSI_A or set to 0b

to ignore PSI_L flag sent through SVI bus.

[8] DPM_ON: Dynamic phase management. It enables or disables

the DPM mode. Set to 1b to enable DPM or set to 0b (default) to

disable it.

When enabled DPM acts automatically cutting phases according to

PSI action flag at light load.

See Section 6.2 for details about DPM.

Table 12.

Power manager I2C command phase and data stream

Command

code [4:6]

Data stream

[1:8]

Description

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