CS43L41

8

DS473PP1

Notes: 9. In Internal SCLK Mode, the Duty Cycle must be 50% ±1/2 MCLK Period.

10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK

ratio. (See Figures 20-26)

Parameters

Symbol

Min

Typ

Max

Units

Input Sample Rate

Fs

2

-

100

kHz

MCLK Pulse Width High

MCLK/LRCK = 512

10

-

1000

ns

MCLK Pulse Width Low

MCLK/LRCK = 512

10

-

1000

ns

MCLK Pulse Width High MCLK / LRCK = 384 or 192

21

-

1000

ns

MCLK Pulse Width Low

MCLK / LRCK = 384 or 192

21

-

1000

ns

MCLK Pulse Width High MCLK / LRCK = 256 or 128

31

-

1000

ns

MCLK Pulse Width Low

MCLK / LRCK = 256 or 128

31

-

1000

ns

External SCLK Mode

LRCK Duty Cycle (External SCLK only)

40

50

60

%

SCLK Pulse Width Low

20

-

-

ns

SCLK Pulse Width High

20

-

-

ns

SCLK Period

MCLK / LRCK = 512, 256 or 384

--

ns

SCLK Period

MCLK / LRCK = 128 or 192

--

ns

SCLK rising to LRCK edge delay

20

-

-

ns

SCLK rising to LRCK edge setup time

20

-

-

ns

SDATA valid to SCLK rising setup time

20

-

-

ns

SCLK rising to SDATA hold time

20

-

-

ns

Internal SCLK Mode

LRCK Duty Cycle (Internal SCLK only)

(Note 9)

-

50

-

%

SCLK Period

(Note 10)

--

ns

SCLK rising to LRCK edge

--

µs

SDATA valid to SCLK rising setup time

--

ns

SCLK rising to SDATA hold time

MCLK / LRCK = 512, 256 or 128

--

ns

SCLK rising to SDATA hold time

MCLK / LRCK = 384 or 192

--

ns

1

128

()Fs

----------------------

1

64

()Fs

------------------

1

SCLK

----------------

tsclkw

2

------------------

1

512

()Fs

----------------------10

+

1

512

()Fs

----------------------15

+

1

384

()Fs

----------------------15

+