CS43L41 datasheet(25/36 Pages) CIRRUS

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CS43L41

DS473PP1

6. APPLICATIONS

6.1

Grounding and Power Supply

Decoupling

As with any high resolution converter, the

CS43L41 requires careful attention to power sup-

ply and grounding arrangements to optimize per-

formance. Figure 6 shows the recommended power

arrangement with VA connected to a clean supply.

Decoupling capacitors should be located as close to

the device package as possible.

6.2

Oversampling Modes

The CS43L41 operates in one of two oversampling

modes based on the input sample rate and the state

of the MCLKDIV bit in the MCLK Control Regis-

ter. Base Rate Mode (BRM) supports input sample

rates up to 50 kHz while High Rate Mode (HRM)

supports input sample rates up to 100 kHz. When

the MCLKDIV bit is cleared, the devices operate in

BRM when MCLK/LRCK is 256, 384 or 512 and

in HRM when MCLK/LRCK is 128 or 192. When

the MCLKDIV bit is set, the devices operate in

BRM when MCLK/LRCK is 512, 768 or 1024 and

in HRM when MCLK/LRCK is 256 or 384.

6.3

Recommended Power-up Sequence

1. Hold RST low until the power supply, master,

and left/right clocks are stable. In this state, the

control port is reset to its default settings and VQ

will remain low.

2. Bring RST high. The device will remain in a low

power state with VQ low and the control port acces-

sible. The desired register settings can be loaded

while keeping the PDN bit set to 1.

3. Set the PDN bit to 0 which will initiate the pow-

er-up sequence, which requires approximately 50

µs when the POR bit is set to 0. If the POR bit is

set to 1, see Section 6.4 for total power-up timing.

6.4

Use of the Power ON/OFF Quiescent

Voltage Ramp

The CS43L41 uses a novel technique to minimize

the effects of output transients during power-up

and power-down. This technique, when used with

external DC-blocking capacitors in series with the

audio outputs, minimizes the audio transients com-

monly produced by single-ended single-supply

converters.

When the device is initially powered-up, the audio

outputs, AOUTA and AOUTB, are clamped to

AGND. Following a delay of approximately 1000

sample periods, each output begins to ramp toward

the quiescent voltage. Approximately 10,000

left/right clock cycles later, the outputs reach VQ

and audio output begins. This gradual voltage

ramping allows time for the external DC-blocking

capacitor to charge to the quiescent voltage, mini-

mizing the power-up transient.

To prevent transients at power-down, the device

must first enter its power-down state. When this oc-

curs, audio output ceases and the internal output

buffers are disconnected from AOUTA and

AOUTB. In their place, a soft-start current sink is

substituted which allows the DC-blocking capaci-

tors to slowly discharge. Once this charge is dissi-

pated, the power to the device may be turned off

and the system is ready for the next power-on.

To prevent an audio transient at the next power-on,

it is necessary to ensure that the DC-blocking ca-

pacitors have fully discharged before turning off

the power or exiting the power-down state. If not, a

transient will occur when the audio outputs are ini-

tially clamped to AGND. The time that the device

must remain in the power-down state is related to

the value of the DC-blocking capacitance. For ex-

ample, with a 3.3 µF capacitor, the minimum pow-

er-down time will be approximately 0.4 seconds.

Use of the Mute Control function is recommended

for designs requiring the absolute minimum in ex-

traneous clicks and pops. Also, use of the Mute

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