CS43L41

DS473PP1

3

Confidential Draft

9/23/99

Positive Voltage Reference - FILT+........................................................................................ 22

Quiescent Voltage - VQ ..........................................................................................................22

Master Clock - MCLK .............................................................................................................23

Left/Right Clock - LRCK .........................................................................................................23

Serial Audio Data - SDATA .................................................................................................... 23

Serial Clock - SCLK ................................................................................................................ 24

Reset - RST ............................................................................................................................ 24

Serial Control Interface Clock - SCL/CCLK ........................................................................... 24

Serial Control Data I/O - SDA/CDIN ....................................................................................... 24

Address Bit / Chip Select - AD0/CS........................................................................................ 24

Mute Control - MUTEC ........................................................................................................... 24

6. APPLICATIONS ..................................................................................................................... 25

6.1 Grounding and Power Supply Decoupling ....................................................................... 25

6.2 Oversampling Modes ....................................................................................................... 25

6.3 Recommended Power-up Sequence ............................................................................... 25

6.4 Use of the Power ON/OFF Quiescent Voltage Ramp ..................................................... 25

7. CONTROL PORT INTERFACE .............................................................................................. 26

7.1 SPI Mode ......................................................................................................................... 26

7.3 Memory Address Pointer (MAP) ....................................................................................... 27

8. PARAMETER DEFINITIONS .................................................................................................. 33

Total Harmonic Distortion + Noise (THD+N) .......................................................................... 33

Dynamic Range ...................................................................................................................... 33

Interchannel Isolation ............................................................................................................. 33

Interchannel Gain Mismatch ................................................................................................... 33

Gain Error ............................................................................................................................... 33

Gain Drift ................................................................................................................................ 33

9. REFERENCES ........................................................................................................................ 33

10. PACKAGE DIMENSIONS .................................................................................................... 34