NG80960JS25 datasheet(19/86 Pages) INTEL

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80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor

Datasheet

BE[3:0]#

R(1)

H(Z)

P(1)

BYTE ENABLES select which of up to four data bytes on the bus participate in the

current bus access. Byte enable encoding is dependent on the bus width of the

memory region accessed:

32-bit bus:

BE3# enables data on AD[31:24]

BE2# enables data on AD[23:16]

BE1# enables data on AD[15:8]

BE0# enables data on AD[7:0]

16-bit bus:

BE3# becomes Byte High Enable (enables data on AD[15:8])

BE2# is not used (state is high)

BE1# becomes Address Bit 1 (A1)

BE0# becomes Byte Low Enable (enables data on AD[7:0])

8-bit bus:

BE3# is not used (state is high)

BE2# is not used (state is high)

BE1# becomes Address Bit 1 (A1)

BE0# becomes Address Bit 0 (A0)

The processor asserts byte enables, byte high enable and byte low enable during Ta.

Since unaligned bus requests are split into separate bus transactions, these signals

do not toggle during a burst. They remain active through the last Td cycle.

For accesses to 8- and 16-bit memory, the processor asserts the address bits in

conjunction with A[3:2] described above.

WIDTH/

HLTD[1:0]

R(0)

H(Z)

P(1)

WIDTH/HALTED signals denote the physical memory attributes for a bus

transaction:

WIDTH/

HLTD1

WIDTH/

HLTD0

8 Bits Wide

16 Bits Wide

32 Bits Wide

Processor Halted

The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in

response to a HOLD request, regardless of prior operating state.

D/C#

R(X)

H(Z)

P(Q)

DATA/CODE indicates that a bus access is a data access (1) or an instruction

access (0). D/C# has the same timing as W/R#.

0 = instruction access

1 = data access

W/R#

R(0)

H(Z)

P(Q)

WRITE/READ specifies, during a Ta cycle, whether the operation is a write (1) or

read (0). It is latched on-chip and remains valid during Td cycles.

0 = read

1 = write

DT/R#

R(0)

H(Z)

P(Q)

DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the

address/data bus. It is low during Ta and Tw/Td cycles for a read; it is high during Ta

and Tw/Td cycles for a write. DT/R# never changes state when DEN# is asserted.

0 = receive

1 = transmit

Table 8.

Pin Description—External Bus Signals (Sheet 2 of 4)

NAME

TYPE

DESCRIPTION

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