TSB41AB2PAPG4 datasheet(32/55 Pages) TI1

32 / 55 page

TSB41AB2, TSB41AB2I

IEEE 1394a2000 TWOPORT CABLE

TRANSCEIVER/ARBITER

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

PHY-Link layer interface (continued)

The PHY may initiate a status transfer either autonomously or in response to a register read request from the

LLC.

The PHY initiates a receive operation whenever a packet is received from the serial bus.

The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the LLC.

The transmit operation is initiated when the PHY grants control of the interface to the LLC.

The encoding of the CTL0 −CTL1 bus is shown in Table 10 and Table 11.

Table 10. CTL Encoding When PHY Has Control of the Bus

CTL0

CTL1

NAME

DESCRIPTION

Idle

No activity (this is the default mode)

Status

Status information is being sent from the PHY to the LLC.

Receive

An incoming packet is being sent from the PHY to the LLC.

Grant

The LLC has been given control of the bus to send an outgoing packet.

Table 11. CTL Encoding When LLC Has Control of the Bus

CTL0

CTL1

NAME

DESCRIPTION

Idle

The LLC releases the bus (transmission has been completed).

Hold

The LLC is holding the bus while data is being prepared for transmission, or indicating that another packet

is to be transmitted (concatenated) without arbitrating.

Transmit

An outgoing packet is being sent from the LLC to the PHY.

Reserved

None

output differentiation

When an Annex J type isolation barrier is implemented between the PHY and LLC, the CTL0 – CTL1, D0 – D7,

and LREQ signals must be digitally differentiated so that the isolation circuits function correctly. Digital

differentiation is enabled on the TSB41AB2 when the ISO terminal is low.

The differentiation operates such that the output is driven either low or high for one clock period whenever the

signal changes logic state, but otherwise places the output in a high-impedance state for as long as the signal

logic state remains constant. On input, hysteresis buffers are used to convert the signal to the correct logic state

when the signal is high impedance; the biasing network of the Annex J type isolation circuit pulls the signal

voltage level between the hysteresis thresholds of the input buffer so that the previous logic state is maintained.

The correspondence between the output logic state and the output signal level is shown in Figure 14.

Logic State

Signal Level

Figure 14. Signal Transformation for Digital Differentiation

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