TSB41AB2PAPG4 datasheet(45/55 Pages) TI1

45 / 55 page

TSB41AB2, TSB41AB2I

IEEE 1394a2000 TWOPORT CABLE

TRANSCEIVER/ARBITER

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

interface reset and disable (continued)

LPS

CTL0, CTL1

LREQ

SYSCLK

(3)

(2)

(1)

D0− D7

(high)

(4)

TLPS_RESET

TLPS_DISABLE

ISO

Figure 25. Interface Disable, ISO High

The sequence of events for disabling the PHY-LLC interface when it is in the nondifferentiated mode of operation

(ISO terminal is high) is as follows:

Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet data

reception and transmission via the CTL and D lines, and request activity via the LREQ line.

LPS deasserted. The LLC deasserts the LPS signal and, within 1

µs, terminates any request or interface

bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.

Interface reset. After TLPS_RESET time, the PHY determines that LPS is inactive, terminates any interface

bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state.

Interface disabled. If the LPS signal remains inactive for TLPS_DISABLE time, the PHY terminates SYSCLK

activity by driving the SYSCLK output low. The PHY-LLC interface is now in the disabled state.

After the interface has been reset, or reset and then disabled, the interface is initialized and restored to normal

operation when LPS is reasserted by the LLC. The timing for interface initialization is shown in Figure 26 and

Figure 27.

TSB41AB2PAPG4 データシート(PDF) 45 Page - Texas Instruments

TSB41AB2PAPG4 データシート(HTML) 45 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

データシートダウンロード