TSB41AB2PAPG4 datasheet(13/55 Pages) TI1

13 / 55 page

TSB41AB2, TSB41AB2I

IEEE 1394a2000 TWOPORT CABLE

TRANSCEIVER/ARBITER

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of operating conditions (unless otherwise

noted) (continued)

device

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

See Note 2

IDD

Supply current

See Note 3

IDD

Supply current

See Note 4

IDD(ULP)

Supply current, ultralow-power mode

VDD = 3.3 V, TA = 25°C,

Port disabled, PD = 0 V,

LPS = 0 V

150

µA

IDD(PD)

Supply current, power-down mode

PD = VDD,VDD = 3.3 V,

TA = 25°C

150

µA

V(TH)

Power status threshold, CPS input†

400-k

Ω resistor†

4.7

7.5

High-level output voltage, CTL0, CTL1,

VDD = 2.7 V, IOH = − 4 mA

2.2

VOH

High-level output voltage, CTL0, CTL1,

D0 − D7, CNA, C/LKON, SYSCLK outputs

VDD = 3 V to 3.6 V,

IOH = − 4 mA

2.8

VOL

Low-level output voltage, CTL0, CTL1,

D0 − D7, CNA, C/LKON, SYSCLK outputs

IOL = 4 mA

0.4

VOH(AJ)

High-level Annex J output voltage, CTL0,

CTL1, D0 − D7, C/LKON, SYSCLK outputs

Annex J: IOH = − 9 mA,

ISO = 0 V,

VDD ≥ 3 V

VDD−0.4

VOL(AJ)

Low-level Annex J output voltage, CTL0,

CTL1, D0−D7, C/LKON, SYSCLK outputs

Annex J: IOL = 9 mA,

ISO = 0 V,

VDD ≥ 3 V

0.4

I(BH+)

Positive peak bus holder current, D0 − D7,

CTL0 − CTL1, LREQ

ISO = 3.6 V,

VDD = 3.6 V,

VI = 0 V to VDD

0.05

I(BH−)

Negative peak bus holder current,

D0 − D7, CTL0 − CTL1, LREQ

ISO = 3.6 V,

VDD = 3.6 V,

VI = 0 V to VDD

−1.0

−0.05

Input current, LREQ, LPS, PD, TESTM,

SM, PC0 – PC2 inputs

ISO = 0 V,

VDD = 3.6 V

µA

IOZ

Off-state output current, CTL0, CTL1,

D0 – D7, C/LKON I/Os

VO = VDD or 0 V

±5

µA

I(IRST)

Pullup current, RESET input

VI = 1.5 V or 0 V

−90

−20

µA

I(SE_Pd)

Pulldown current, SE input

VI = VDD/2 or VDD

µA

VIT+

Positive input threshold voltage, LREQ,

CTL0, CTL1, D0 – D7 inputs

ISO = 0 V,

VDD = 3V to 3.6 V

VDD/2+0.3

VDD/2+0.9

VIT+

Positive input threshold voltage, LPS

inputs

ISO = 0 V, VDD = 3 V to 3.6 V

Vref = 0.42 VDD

VREF+1

VIT −

Negative input threshold voltage, LREQ,

CTL0, CTL1, D0 – D7 inputs

ISO= 0 V,

VDD = 3 V to 3.6 V

VDD/2−0.9

VDD/2−0.3

VIT −

Negative input threshold voltage, LPS

inputs

ISO= 0 V,

Vref = 0.42 VDD,

VDD = 3 V to 3.6 V

Vref+0.2

TPBIAS output voltage‡

At rated IO current

1.665

2.015

† Measured at cable power side of resistor

‡ TPBIAS is close to VDD when the port is not connected.

NOTES:

2. Transmit maximum packet (all ports transmitting maximum size isochronous packet – 4096 bytes, sent on every isochronous

interval, S400, data value of CCCCCCCCh), VDD = 3.3 V, TA = 25°C.

3. Repeat typical packet (receiving on one port DV packets on every isochronous interval, S100, and transmitting on the other port),

VDD = 3.3 V, TA = 25°C.

4. Idle (one port receiving and one port transmitting cycle starts), VDD = 3.3 V, TA = 25°C.

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