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82C55 データシート(PDF) 13 Page - Intel Corporation

部品番号 82C55
部品情報  CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
PDF  23 Pages
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メーカー  INTEL [Intel Corporation]
ホームページ  http://www.intel.com
Logo INTEL - Intel Corporation

82C55 データシート(HTML) 13 Page - Intel Corporation

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82C55A
Combinations of MODE 1
Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed
IO applications
231256 – 17
Figure 12 Combinations of MODE 1
Operating Modes
MODE 2 (Strobed Bidirectional Bus IO)
This
functional configuration provides a means for com-
municating with a peripheral device or structure on a
single 8-bit bus for both transmitting and receiving
data (bidirectional bus IO) ‘‘Handshaking’’ signals
are provided to maintain proper bus flow discipline in
a similar manner to MODE 1 Interrupt generation
and enabledisable functions are also available
MODE 2 Basic Functional Definitions
 Used in Group A only
 One 8-bit bi-directional bus port (Port A) and a 5-
bit control port (Port C)
 Both inputs and outputs are latched
 The 5-bit control port (Port C) is used for control
and status for the 8-bit bi-directional bus port
(Port A)
Bidirectional Bus IO Control Signal Definition
INTR (Interrupt Request)
A high on this output can
be used to interrupt the CPU for input or output oper-
ations
Output Operations
OBF (Output Buffer Full)
The OBF output will go
‘‘low’’ to indicate that the CPU has written data out
to port A
ACK (Acknowledge)
A ‘‘low’’ on this input enables
the tri-state output buffer of Port A to send out the
data Otherwise the output buffer will be in the high
impedance state
INTE 1 (The INTE Flip-Flop Associated with
OBF)
Controlled by bit setreset of PC6
Input Operations
STB (Strobe Input)
A ‘‘low’’ on this input loads
data into the input latch
IBF (Input Buffer Full FF)
A ‘‘high’’ on this output
indicates that data has been loaded into the input
latch
INTE 2 (The INTE Flip-Flop Associated with IBF)
Controlled by bit setreset of PC4
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