AN3427 datasheet(21/52 Pages) STMICROELECTRONICS

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AN3427

Peripheral migration

Doc ID 019001 Rev 1

21/52

To configure the access to a given peripheral you have first to know to which bus this

peripheral is connected, refer to Table 3 on page 13, then depending on the action needed

you have to program the right register as described in Table 6. above. For example, USART1

is connected to APB2 bus, to enable the USART1 clock you have to configure the

APB2ENR register as follows:

RCC->APB2ENR |= RCC_APB2ENR_USART1EN;

to disable USART1 clock during Sleep mode (to reduce power consumption) you have to

configure APB2LPENR register as follows:

RCC->APB2LPENR |= RCC_APB2LPENR_USART1LPEN;

Peripheral clock configuration: some peripherals have a dedicated clock source

independent from the system clock, and used to generate the clock required for their

operation::

I2S: in the F2 series the I2S clock can be derived either from a specific PLL

(PLLI2S) or from an external clock mapped on the I2S_CKIN pin:

To use PLLI2S as I2S clock source: set RCC_CFGR[I2SSRC] bit to 1, configure

the PLLI2S parameters (using RCC_PLLI2SCFGR[PLLI2SR] and

RCC_PLLI2SCFGR[PLLI2SN] bits) then enable it (set RCC_CR[PLLI2SON] bit to

Table 6.

RCC registers used for peripheral access configuration

Bus

Comments

AHB1

RCC_AHB1RSTR

Used to [enter/exit] the AHB1peripheral from reset

RCC_AHB1ENR

Used to [enable/disable] the AHB1 peripheral clock

RCC_AHB1LPENR

Used to [enable/disable] the AHB1 peripheral clock in low

power Sleep mode

AHB2

RCC_AHB2RSTR

Used to [enter/exit] the AHB2 peripheral from reset

RCC_AHB2ENR

Used to [enable/disable] the AHB2 peripheral clock

RCC_AHB2LPENR

Used to [enable/disable] the AHB2 peripheral clock in low

power Sleep mode

AHB3

RCC_AHB3RSTR

Used to [enter/exit] the AHB3 peripheral from reset

RCC_AHB3ENR

Used to [enable/disable] the AHB3 peripheral clock

RCC_AHB3LPENR

Used to [enable/disable] the AHB3 peripheral clock in low

power Sleep mode

APB1

RCC_APB1RSTR

Used to [enter/exit] the APB1 peripheral from reset

RCC_APB1ENR

Used to [enable/disable] the APB1 peripheral clock

RCC_APB1LPENR

Used to [enable/disable] the APB1 peripheral clock in low

power Sleep mode

APB2

RCC_APB2RSTR

Used to [enter/exit] the APB2 peripheral from reset

RCC_APB2ENR

Used to [enable/disable] the APB2 peripheral clock

RCC_APB2LPENR

Used to [enable/disable] the APB2 peripheral clock in low

power Sleep mode

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