RM0312 datasheet(133/275 Pages) STMICROELECTRONICS

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RM0312

16-bit general purpose timer (TIM2/TIM3)

170

Figure 55. Output stage of channel 1

17.5.5

Forced output mode

In output mode (CCiS bits = 0b00 in the TIMx_CCMRi register) where i is the channel

number, each output compare signal can be forced to high or low level directly by software,

independently of any comparison between the output compare register and the counter.

To force an output compare signal to its active level, you just need to write ‘101’ in the OCiM

bits in the corresponding TIMx_CCMRi register. Thus OCiREF is forced high (OCiREF is

always active high) and the OCi output is forced to high or low level depending on the CCiP

polarity bit.

For example: CCiP=0 (OCi active high) => OCi is forced to high level.

The OCiREF signal can be forced low by writing the OCiM bits to 0b100 in the

TIMx_CCMRx register.

Anyway, the comparison between the TIMx_CCRi shadow register and the counter is still

performed and allows the flag to be set. Interrupt requests can be sent accordingly. This is

described in the Output Compare Mode section below.

17.5.6

Output compare mode

This function is used to control an output waveform or indicate when a period of time has

elapsed.

When a match is found between the capture/compare register and the counter:

•

Depending on the output compare mode, the corresponding OCi output pin:

–

keeps its level (OCiM=0b000),

–

is set active (OCiM=0b001),

–

is set inactive (OCiM=0b010)

–

or toggles (OCiM=0b011)

•

Sets a flag in the interrupt status register (CCiIF bit in the TIMx_SR1 register).

•

Generates an interrupt if the corresponding interrupt mask is set (CCiIE bit in the

TIMx_IER register).

The output compare mode is defined by the OCiM bits in the TIMx_CCMRi register. The

active or inactive level polarity is defined by the CCiP bit in the TIMx_CCERi register.

Output Mode

Counter

> CCR1

Counter

= CCR1

Controller

TIMx_CCMR1

OC1M[2:0]

OC1REF

CC1P

TIMx_CCER1

Output

Enable

Circuit

OC1

CC1E TIMx_CCER1

ETR

OSSI

TIMx_BKR

MOE

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