RM0312 datasheet(130/275 Pages) STMICROELECTRONICS

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16-bit general purpose timer (TIM2/TIM3)

RM0312

130/275

DocID022352 Rev 3

Figure 51. Input stage of TIM 1 channel 1

17.5.3

Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRi) are used to latch the

value of the counter after a transition detected on the corresponding ICi signal. When a

capture occurs, the corresponding CCiIF flag (TIMx_SR1 register) is set.

An interrupt can be sent if it is enabled by setting the CCiIE bit in the TIMx_IER register. If a

capture occurs while the CCiIF flag was already high, then the over-capture flag CCiOF

(TIMx_SR2 register) is set. CCiIF can be cleared by software by writing it to ‘0’ or by reading

the captured data stored in the TIMx_CCRiL register. CCiOF is cleared when you write it to

‘0’.

The following example shows how to capture the counter value in TIMx_CCR1 when TI1

input rises. To do this, use the following procedure:

Select the active input: For example, to link the TIMx_CCR1 register to the TI1 input,

write the CC1S bits to 0b01 in the TIMx_CCMR1 register. This configures the channel

in input mode and the TIMx_CCR1 register becomes read-only.

Program the input filter duration that is needed for the type of the signal to be

conntected to the timer. This is done for each TIi input using the ICiF bits in the

TIMx_CCMRi register. For example, if you know that when, the input signal toggles, it

is unstable for up to 5 fMASTER cycles, you must program the filter duration longer than

5 clock cycles. The filter bits allow you to select a duration of 8 cycles by writing the

value 0b0011 in in these bits the TIMx_CCMR1 register. With this filter setting, a

transition on TI1 is valid only when 8 consecutive samples with the new level have

been detected (sampled at fMASTER frequency).

Select the edge of the active transition on the TI1 channel by writing CC1P bit to ‘0’ in

the TIMx_CCER1 register (rising edge in this case).

Program the input prescaler. In our example, we want the capture to be performed at

each valid transition, so the prescaler is disabled (write IC1PS bits to 0b00 in the

TIMx_CCMR1 register).

Enable capture from the counter into the capture register by setting the CC1E bit in the

TIMx_CCER1 register.

If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_IER

TI1

TIMx_CCER1

CC1P

divider

/1, /2, /4, /8

ICPS[1:0]

TI1F_ED

filter

ICF[3:0]

down-counter

TIMx_CCMR1

Edge

Detector

TI1F_rising

TI1F_falling

to clock/trigger controller

TI1FP1

TIMx_CCMR1

CC1S[1:0]

IC1

TI2FP1

TRC

(from channel 2)

(from clock/trigger

controller)

fMASTER

TIMx_CCER1

CC1E

ICPS

TI1F

TI2F_rising

TI2F_falling

(from channel 2)

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