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RM0312 データシート(PDF) 228 Page - STMicroelectronics |
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RM0312 データシート(HTML) 228 Page - STMicroelectronics |
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228 / 275 page  Universal synchronous/asynchronous receiver transmitter (USART) RM0312 228/275 DocID022352 Rev 3 21.3.1 USART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the USART_CR1 register (see Figure 82). The USART_TX pin is in low state during the start bit. It is in high state during the STOP bit. An Idle character is interpreted as an entire frame of “1”s (the number of “1” ‘s includes the start bit, the number of data bits and the number of STOP bits). A Break character is interpreted on receiving “0”s for a frame period. At the end of the break frame the transmitter inserts either 1 or 2 STOP bits (logic “1” bit) to acknowledge the start bit. Transmission and reception are driven by a common baud rate generator, the clock for each is generated when the enable bit is set respectively for the transmitter and receiver. The details of each block is given below. Figure 82. Word length programming Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Start Bit STOP Bit Next Start Bit Idle Frame Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Start Bit STOP Bit Next Start Bit Idle frame Start Bit 9-bit word length (M bit is set), 1 STOP bit 8-bit word length (M bit is reset), 1 STOP bit Possible parity bit Possible Parity Bit Break Frame Start Bit Extra ’1’ Data Frame Break frame Start Bit Extra ’1’ Data Frame Next data frame Next data frame Start Bit **** ** LBCL bit controls last data clock pulse CLOCK CLOCK ** LBCL bit controls last data clock pulse ** ** |
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