A25LMQ64 datasheet(32/70 Pages) AMICC

32 / 70 page

A25LMQ64 Series

PRELIMINARY

(August, 2014, Version 0.2)

AMIC Technology Corp.

Table 10. Parameter ID (0) (Advanced Information) (continued)

Description

Address (h)

(Byte Mode)

Data

(Bit)

Data

Comment

(1-1-2) Fast Read Number of Wait states (dummy

clocks) needed before valid output

01000b

8 dummy clocks

(1-1-2) Fast Read Number of Mode Bits

3Ch

000b

Not Supported

(1-1-2) Fast Read Opcode

Opcode for single input opcode & address and dual

output data Fast Read.

3Dh

15 : 08

3Bh

(1-2-2) Fast Read Number of Wait states (dummy

clocks) needed before valid output

00100b

4 dummy clocks

(1-2-2) Fast Read Number of Mode Bits

3Eh

000b

Not Supported

(1-2-2) Fast Read Opcode

Opcode for single input opcode, dual input address, and

dual output data Fast Read.

3Fh

31 : 24

BBh

Table 10. Parameter ID (0) (Advanced Information) (continued)

Description

Address (h)

(Byte Mode)

Data

(Bit)

Data

Comment

Supports (4-4-4) Fast Read

Device supports Quad input opcode & address and

quad output data Fast Read.

0 = not supported

1 = supported

Reserved. These bits default to all 1’s

111b

Reserved

Supports (2-2-2) Fast Read

Device supports dual input opcode & address and dual

output data Fast Read.

0 = not supported

1 = supported

Reserved. These bits default to all 1’s

40h

111b

Reserved

Reserved. These bits default to all 1’s

43h : 41h

31 : 08

FFh

Reserved

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