LIS2DS12TR datasheet(25/68 Pages) STMICROELECTRONICS

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LIS2DS12

Digital main blocks

5.3

Data stabilization time vs. ODR setting

The data stabilization time required when an ODR change is applied in order to have valid

usable data depends on the ODR selected and device setting.

The table below provides the number of samples to be discarded in order to obtain valid

usable data.

5.4

FIFO

The LIS2DS12 embeds 256 slots of 14-bit data FIFO for each of the three output channels,

X, Y and Z of the acceleration module. This allows consistent power saving for the system,

since the host processor does not need to continuously poll data from the sensor, but it can

wake up only when needed and burst the significant data out from the FIFO.

The internal FIFO allows collecting 256 samples (14-bit size data) for each axis or storing

the output of the module computation up to 768 samples (14-bit size data).

When the FIFO mode is other than Bypass, reading the output registers (28h to 2Dh)

returns the oldest FIFO sample set. In order to minimize communication between the

master and slave, the address read may be automatically incremented by the device by

setting the IF_ADD_INC bit of CTRL2 (21h) to '1'; the device rolls back to 0x28 when

This buffer can work according to the following 5 different modes:



Bypass mode



FIFO mode



Continuous-to-FIFO



Bypass-to-Continuous



Continuous

Each mode is selected by the FIFO_MODE bits in the FIFO_CTRL (25h) register.

Table 13. Number of samples to be discarded

ODR [Hz]

6400

3200

1600

800

400

200

100

12.5

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