AS3955 datasheet(79/111 Pages) AMSCO

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ams Datasheet

Page 79

[v1-01] 2015-Apr-29

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AS3955 − Register Description

Interrupt Registers

Figure 89:

Mask Interrupt Register 0

Note(s) and/or Footnote(s):

1. The mask bits only mask the triggering of the physical interrupt line. The interrupt bits in the Interrupt register still get set when

the interrupt is masked.

2. Default values are loaded from EEPROM configuration block bits (MIRQ_0).

Figure 90:

Mask Interrupt Register 1

Note(s) and/or Footnote(s):

1. The mask bits only mask the triggering of the physical interrupt line. The interrupt bits in the Interrupt register still get set when

the interrupt is masked.

2. Default values are loaded from EEPROM configuration block bits (MIRQ_1).

Address 08h:

Mask Interrupt 0 (1)

Bit

Name

Default

Function

Type

7M_pu

see note (2)

Mask I_pu IRQ

M_wu_a

Mask I_wu_a IRQ

M_slp

Mask I_slp IRQ

M_eew_rf

Mask I_eew_rf IRQ

M_eer_rf

Mask I_eer_rf IRQ

M_rxe

Mask I_rxe IRQ

M_txe

Mask I_txe IRQ

M_xrf

Mask I_xrf IRQ

Address 09h:

Mask Interrupt 1 (1)

Bit

Name

Default

Function

Type

7M_rxs

see note (2)

Mask I_rxs IRQ

M_frm_err

Mask I_frm_err IRQ

M_par_err

Mask I_par_err IRQ

M_crc_err

Mask I_crc_err IRQ

M_bf_err

Mask I_bf_err IRQ

M_io_eewr

Mask I_io_eewr IRQ

M_eeac_err

Mask I_eeac_err IRQ

M_acc_err

Mask I_acc_err IRQ

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