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POWERSTEP01 データシート(PDF) 19 Page - STMicroelectronics

部品番号 POWERSTEP01
部品情報  System-in-package integrating microstepping controller and 10 A power MOSFETs
PDF  92 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

POWERSTEP01 データシート(HTML) 19 Page - STMicroelectronics

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DocID025022 Rev 5
19/92
powerSTEP01
Pin list
92
12
SDI
Logic input
Data input pin for serial interface
11
CK
Logic input
Serial interface clock
10
CS
Logic input
Chip select input pin for serial interface
15
BUSY
/SYNC
Open-drain
output
By default BUSY/SYNC pin is forced low when the device
is performing a command.
The pin can be programmed in order to generate
a synchronization signal.
16
FLAG
Open-drain
output
Status flag pin. An internal open-drain transistor can pull
the pin to GND when a programmed alarm condition
occurs (step loss, OCD, thermal pre-warning or shutdown,
UVLO, wrong command, non performable command).
19
STBY
/RESET
Logic input
Standby and reset pin. LOW logic level puts the device in
standby mode and reset logic.
If not used, should be connected to VREG
17
STCK
Logic input
Step clock input.
Table 5. Pin description (continued)
No.
Name
Type
Function



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