VNI8200XP-32 datasheet(23/43 Pages) STMICROELECTRONICS

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VNI8200XP-32

Pin function description

DocID027849 Rev 3

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kept low. When counted CLK rising edges are a multiple of 8 and parity check is valid, the

FAULT

pin is kept high.

9.10

Power Good ( PG )

The PG

terminal is an open drain, which indicates the status of the supply voltage. When

VCC supply voltage reaches the Vsth1 threshold, PG goes into a high impedance state. It

goes into a low impedance state when VCC falls below the Vsth2 threshold.

In 16-bit SPI mode, a PG

bit is also available. This bit is set high when the Power Good

diagnostic is active, it is otherwise cleared.

Figure 7: Power Good diagnostic

9.11

Programmable watchdog counter reset (WD)

If SEL2 = H, the VNI8200XP-32 embeds a watchdog counter that must be erased, with a

negative pulse on the WD pin, before it expires. If the WD counter elapses, the

VNI8200XP-32 goes into an internal reset state where all the outputs are disabled; to

restart normal operation a negative pulse must be applied to the WD pin.

The watchdog enable/disable pin should be connected through an external divider to VREG.

The watchdog time is fixed in the following table:

Table 14: Programmable watchdog time

VWD_EN

tWM

0.25 VREG > VWD_EN

Disable

0.25 VREG ≤ VWD_EN < 0.5 VREG

40 ± 25% ms

0.25 VREG ≤ VWD_EN < 0.75 VREG

80 ± 25% ms

0.75 VREG ≤ VWD_EN = VREG

160 ± 25% ms

Vcc

VPGH2

VPGH1

GIPG030420151221LM

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