DP83902AVLC datasheet(37/70 Pages) NSC

37 / 70 page

110 Initialization Procedures

The ST-NIC must be initialized prior to transmission or re-

ception of packets from the network Power on reset is ap-

plied to the ST-NIC’s reset pin This clearssets the follow-

ing bits

Reset Bits

Set Bits

Command Register (CR)

TXP STA

RD2 STP

Interrupt Status (ISR)

RST

Interrupt Mask (IMR)

All Bits

Data Control (DCR)

LAS

Transmit Config (TCR)

LB1 LB0

The ST-NIC remains in its reset state until a Start Command

is issued This guarantees that no packets are transmitted

or received and that the ST-NIC remains a bus slave until all

appropriate internal registers have been programmed After

initialization the STP bit of the command register is reset

and packets may be received and transmitted

Initialization Sequence

The following initialization procedure is mandatory

1 Program Command Register for Page 0 (Command

2 Initialize Data Configuration Register (DCR)

3 Clear Remote Byte Count Registers (RBCR0 RBCR1)

4 Initialize Receive Configuration Register (RCR)

5 Place the ST-NIC in LOOPBACK mode 1 or 2 (Transmit

Configuration Register e 02H or 04H)

6 Initialize

Receive

Buffer

Ring

Boundary

Pointer

(BNDRY)

Page Start (PSTART)

and Page Stop

(PSTOP)

7 Clear Interrupt Status Register (ISR) by writing 0FFH to

8 Initialize Interrupt Mask Register (IMR)

9 Program Command Register for page 1 (Command

I) Initialize Physical Address Registers (PAR0 – PAR5)

II) Initialize Multicast Address Registers (MAR0 – MAR5)

III) Initialize CURRent pointer

10 Put ST-NIC in START mode (Command Register e

22H)

11 Initialize the Transmit Configuration Register for the in-

tended value The ST-NIC is now ready for transmission

and reception

Before receiving packets the user must specify the location

of the Receive Buffer Ring This is programmed in the Page

Start and Page Stop Registers In addition the Boundary

and Current Page Register must be initialized to the value of

the Page Start Register These registers will be modified

during reception of packets

120 Loopback Diagnostics

Three forms of local loopback are provided on the ST-NIC

The user has the ability to loopback through the deserializer

on the controller through the ENDEC module or the Trans-

ceiver Because of the half duplex architecture of the

ST-NIC loopback testing is a special mode of operation

with the following restrictions

Restrictions During Loopback

The FIFO is split into two halves one half is used for trans-

mission and the other for reception Only 8-bit fields can be

fetched from memory so two tests are required for 16-bit

systems to verify integrity of the entire data path During

loopback the maximum latency from the assertion of BREQ

to BACK is 20 ms Systems that wish to use the loopback

test but do not meet this latency can limit the loopback to

7 bytes without experiencing underflow

Only the last

8 bytes of the loopback packet are retained in the FIFO

The last 8 bytes can be read through the FIFO register

which will advance through the FIFO to allow reading the

receive packet sequentially

Destination Address e (6 Bytes) Station Physical Address

Source Address

Length

2 Bytes

Data

46 to 1500 Bytes

CRC

Appended by ST-NIC

if CRC e ‘‘0’’ in TCR

When in word-wide mode with Byte Order Select set the

loopback packet must be assembled in the even byte loca-

tion as shown below (Loopback only operates with byte

wide transfers)

TLF11157 – 54

When in word-wide mode with Byte Order Select low the

following format must be used for the loopback packet

TLF11157 – 55

Note

When using loopback in word mode 2n bytes must be programmed in

TBCR0 1 Where n e actual number of bytes assembled in even or

odd location

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