LM10506_15 datasheet(25/43 Pages) TI1

25 / 43 page

LM10506

www.ti.com

SNVS729F – SEPTEMBER 2011 – REVISED AUGUST 2014

Programming (continued)

ADDR

REG NAME

BIT

R/W

DEFAULT

DESCRIPTION

NOTES

—

LDO OK

LDO is greater than 90% of target

0x0D

Interrupt Status

Buck 3 OK

Buck 3 is greater than 90% of target

Buck 2 OK

Buck 2 is greater than 90% of target

Buck 1 OK

Buck 1 is greater than 90% of target

Comparator

Comparator output is high

—

0x0E

MISC Control

—

R/W

LDO Sleep Mode

LDO goes into extra power save mode

IRQ_polarity = 0

→Active low IRQ

R/W

IRQ Polarity

IRQ_polarity = 1

→Active high IRQ

8.4.1.1.1

ADDR 0x07& 0x08: Buck 1 And Buck 2 Voltage Code And VOUT Level Mapping

VOLTAGE CODE

VOLTAGE (V)

VOLTAGE CODE

VOLTAGE (V)

0x00

1.10

0x20

2.70

0x01

1.15

0x21

2.75

0x02

1.20

0x22

2.80

0x03

1.25

0x23

2.85

0x04

1.30

0x24

2.90

0x05

1.35

0x25

2.95

0x06

1.40

0x26

3.00

0x07

1.45

0x27

3.05

0x08

1.50

0x28

3.10

0x09

1.55

0x29

3.15

0x0A

1.60

0x2A

3.20

0x0B

1.65

0x2B

3.25

0x0C

1.70

0x2C

3.30

0x0D

1.75

0x2D

3.35

0x0E

1.80

0x2E

3.40

0x0F

1.85

0x2F

3.45

0x10

1.90

0x30

3.50

0x11

1.95

0x31

3.55

0x12

2.00

0x32

3.60

0x13

2.05

0x33

3.60

0x14

2.10

0x34

3.60

0x15

2.15

0x35

3.60

0x16

2.20

0x36

3.60

0x17

2.25

0x37

3.60

0x18

2.30

0x38

3.60

0x19

2.35

0x39

3.60

0x1A

2.40

0x3A

3.60

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