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TUSB5052 データシート(PDF) 41 Page - Texas Instruments |
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TUSB5052 データシート(HTML) 41 Page - Texas Instruments |
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41 / 82 page ![]() 5−7 5.12 HUBVIDL: Hub-VID Register (Low-Byte) D7 D6 D5 D4 D3 D2 D1 D0 7 6 5 4 32 10 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 7 D[7:0] 0 Hub VID low-byte value 5.13 HUBVIDH: Hub-VID Register (High-Byte) D7 D6 D5 D4 D3 D2 D1 D0 7 6 5 4 32 10 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 7 D[7:0] 0 Hub VID high-byte value 5.14 Function Reset and Power-Up Reset Interconnect Figure 5−1 represents the logical connection of the USB-function-reset (USBR) and power-up-reset (RSTI) pins. The internal RESET signal is generated from the RSTI pin (PURS signal) or from the USB-reset (USBR signal). The USBR can be enabled or disabled by the FRSTE bit in the USBCTL register (on power-up, FRSTE = 0). The internal RESET is used to reset all registers and logic with the exception of the USBCTL and GLOBCTL registers, which are cleared by the PURS signal only. As shown, the RESET/RESET is connected to the MUX, which controls the RSTO output polarity (the MUX is controlled by the GLOBCTL register). In the development mode, the RSTO signal is used to reset the external microcontroller or other devices. |
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