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TUSB5052 データシート(PDF) 26 Page - Texas Instruments

部品番号 TUSB5052
部品情報  USB TO 2-SERIAL PORT CONTROLLER WITH CONFIGURABLE OPTIONAL HUB
PDF  82 Pages
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

TUSB5052 データシート(HTML) 26 Page - Texas Instruments

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4−6
4.3
Endpoint Descriptor Block (EDB-1 to EDB-7)
Data transfers between the USB, the MCU and external devices are defined by an endpoint descriptor block (EDB).
Eight input- and eight output-EDBs are provided. With the exception of EDB-0 (I/O endpoint_0), all EDBs are located
in SRAM as per Table 4−4. Each EDB contains information describing the X and Y buffers. In addition, each EDB
provides general status information.
Table 4−5 illustrates the EDB entries for EDB-1 to EDB-7. EDB-0 registers are described separately.
Table 4−4. EDB Memory Locations
ADDRESS
REGISTER
DESCRIPTION
FF78
IEPCNF_7
Input endpoint_7: Configuration
FF70
IEPCNF_6
Input endpoint_6: Configuration
FF68
IEPCNF_5
Input endpoint_5: Configuration
FF60
IEPCNF_4
Input endpoint_4: Configuration
FF58
IEPCNF_3
Input endpoint_3: Configuration
FF50
IEPCNF_2
Input endpoint_2: Configuration
FF48
IEPCNF_1
Input endpoint_1: Configuration
FF47
↑
RESERVED
FF40
FF38
OEPCNF_7
Output endpoint_7: Configuration
FF30
OEPCNF_6
Output endpoint_6: Configuration
FF28
OEPCNF_5
Output endpoint_5: Configuration
FF20
OEPCNF_4
Output endpoint_4: Configuration
FF18
OEPCNF_3
Output endpoint_3: Configuration
FF10
OEPCNF_2
Output endpoint_2: Configuration
FF08
OEPCNF_1
Output endpoint_1: Configuration
FF07
↑
(8-bytes)
FF00
Setup packet block
FEFF
↑
(8-bytes)
FEF8
Input endpoint_0 buffer
FEF7
↑
(8-bytes)
FEF0
Output endpoint_0 buffer
FEEF
TOPBUFF
Top of buffer space
↑
Buffer space
F800
STABUFF
Start of buffer space



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