TUSB5052 datasheet(46/82 Pages) TI

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6−4

6.1.3

DMACDR[4:3]: DMA Channel Definition Register (2 UART Receive Channels)

These registers are used to define the EDB number that the DMA uses for data transfer to the UARTs. In addition,

these registers define the data transfer direction and select X or Y as the transaction buffer.

5432

INE

CNT

XY_WR_PROT

R/W

BIT

NAME

RESET

FUNCTION

2−0

E[2:0]

Endpoint descriptor pointer. This field points to a set of EDB registers that is to be used for a given transfer.

XY_WR_PROT

XY protection bit. This bit always returns 1 when read. If this bit is 1 during a write, XY (bit 4) is not affected. If

this bit is 0 during a write, the value of XY is loaded from MCU bit 4.

XY buffer select bit. Valid only when CNT = 0

XY = 0 Next buffer to transmit/receive is X

XY = 1 Next buffer to transmit/receive is Y

CNT

DMA continuous transfer control bit. This bit defines the mode of the DMA transfer.

CNT

CNT = 0

Burst Mode: DMA stops the transfer when the byte count = 0 or when a receiver error occurs. At

the end of transfer, the high-to-low transition of EN interrupts the MCU (if enabled). In this mode,

the XY bit is set by the MCU to define the current buffer (X or Y). Single buffering is required in this

mode.

CNT = 1

Continuous Mode: In this mode, the DMA and UBM alternate between the X and Y buffers. The

UBM sets the XY bit and the DMA uses it for the transfer. The DMA alternates between the

X/Y-buffers and continues transmitting (from X/Y buffer) without MCU intervention. The DMA

terminates, and interrupts the MCU, under the following conditions:

1. Transaction time-out expired: DMA updates EDB and interrupts the MCU. UBM transfers the

partial packet to host.

2. UART receiver error condition: DMA updates EDB and does not interrupt the MCU. UBM

transfers the partial packet to host.

INE

DMA interrupt enable/disable bit. This bit is used to enable/disable the interrupt on transfer completion.

INE

INE = 0

Interrupt is disabled. In addition, OVRUN and TXFT do not clear the EN bit and the DMAC is not

disabled.

INE = 1

Enables the EN interrupt. When this bit is set, the DMA interrupts the MCU on a 1-to-0 transition

of the EN bit. (When transfer is completed, EN = 0)

DMA channel enable bit. The MCU sets this bit to start the DMA transfer. When the transfer completes, or

when it is terminated due to error, this bit is cleared. The 1-to-0 transition of this bit generates an interrupt (if

interrupt is enabled).

EN = 0

DMA is halted. The DMA is halted when transaction time-out occurs, or under a UART

receiver-error condition. When halted, the DMA updates the byte-count and sets NAK = 0 in

IEDB. If the termination is due to transaction time-out, the DMA generates an interrupt. However,

if the termination is due to a UART error condition, the DMA does not generate an interrupt. (The

UART generates the interrupt.)

EN = 1

Setting this bit starts the DMA transfer.

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