AD6634BCSLASHPCB datasheet(39/52 Pages) AD

39 / 52 page

REV. 0

AD6634

–39–

0x90: rCIC2 Decimation – 1 (MrCIC2 – 1)

This register is used to set the decimation in the rCIC2 filter.

The value written to this register is the decimation minus one.

The rCIC2 decimation can range from 1 to 4096, depending

upon the interpolation of the channel. The decimation must

always be greater than the interpolation. MrCIC2 must be chosen

larger than LrCIC2 and both must be chosen such that a suitable

rCIC2 scalar can be chosen. For more details, the rCIC2 section

should be consulted.

0x91: rCIC2 Interpolation – 1 (LrCIC2 – 1)

This register is used to set the interpolation in the rCIC2 filter.

The value written to this register is the interpolation minus one.

The rCIC2 interpolation can range from 1 to 512, depending

upon the decimation of the rCIC2. There is no timing error

associated with this interpolation. See the rCIC2 section for

further details.

0x92: rCIC2 Scale

The rCIC2 scale register is used to provide attenuation to com-

pensate for the gain of the rCIC2 and to adjust the linearization

of the data from the floating-point input. The use of this scale

point input port considerations. The rCIC2 section should be

consulted for details. The rCIC2 scalar has been combined with

the exponent offset and will need to be handled appropriately in

both the input port and rCIC2 sections.

Bit 11 determines the polarity of the exponent. Normally, this

bit will be cleared unless an ADC such as the AD6600 is used,

in which case this bit will be set.

Bit 10 determines the weight of the exponent word associated

with the input port. When this bit is Low, each exponent step is

considered to be worth 6.02 dB. When this bit is High, each

exponent step is considered to be worth 12.02 dB.

Table XI. Channel Address Memory Map

Channel

Bit

Address

Width

Comments

rCIC2 Decimation – 1

MrCIC2–1

rCIC2 Decimation – 1

LrCIC2–1

rCIC2 Scale

11: Exponent Invert

10: Exponent Weight

9–5: rCIC2_QUIET[4:0]

4–0: rCIC2_LOUD[4:0]

Reserved

Reserved (Must Be Written Low)

CIC5 Decimation – 1

MCIC5–1

CIC5 Scale

4–0: CIC5_SCALE[4:0]

Reserved

Reserved (Must Be Written Low)

97–9F

Unused

RCF Decimation – 1

MRCF–1

RCF Decimation Phase

PRCF

RCF Number of Taps – 1

NTAPS–1

RCF Coefficient Offset

CORCF

RCF Control Register

10: RCF Bypass BIST

9: RCF Input Select

(Own 0, Other 1)

8: Program RAM Bank 1/0

7: Use Common Exponent

6: Force Output Scale

5–4: Output Format

1x: Floating Point 12 + 4

01: Floating Point 8 + 4

00: Fixed Point

3–0:1Output Scale

BIST Signature for I Path

BIST-I

BIST Signature for Q Path

BIST-Q

No. of BIST Outputs to

Accumulate

19–0: No. of Outputs(Counter Value Read)

RAM BIST Control Register

2: D-RAM Fail/Pass

1: NC-RAM Fail/Pass

0: RAM BIST Enable

Output Control Register

9: Map RCF Data to BIST Registers

5: Output Format

1:16-Bit I and 16-Bit Q

0:12-Bit I and 12-Bit Q

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