PDI1394L40 datasheet(69/80 Pages) PHILIPS

69 / 80 page

Philips Semiconductors

Preliminary specification

PDI1394L40

1394 enhanced AV link layer controller

2000 Dec 15

13.5.1.2

Asynchronous Receive Request FIFO Size (RREQSIZE) – Indirect Address: 0x104

SV01767

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11

base_fifo

end_fifo

Reset Value 0x00000407

Bit 31..14

R/W

Unused bits read ‘0’

Bit 13..8

R/W

base_fifo: Base address of the FIFO

Bit 7, 6

R/W

Unused bits read ‘0’

Bit 5..0

R/W

end_fifo: End address of the FIFO

13.5.1.3

Asynchronous Transmit Response FIFO Size (TRSPSIZE) – Indirect Address: 0x110

SV01768

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11

base_fifo

end_fifo

Reset Value 0x0000080B

Bit 31..14

R/W

Unused bits read ‘0’

Bit 13..8

R/W

base_fifo: Base address of the FIFO

Bit 7, 6

R/W

Unused bits read ‘0’

Bit 5..0

R/W

end_fifo: End address of the FIFO

13.5.1.4

Asynchronous Transmit Request FIFO Size (TREQSIZE) – Indirect Address: 0x114

SV01769

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11

base_fifo

end_fifo

Reset Value 0x00000C0F

Bit 31..14

R/W

Unused bits read ‘0’

Bit 13..8

R/W

base_fifo: Base address of the FIFO

Bit 7, 6

R/W

Unused bits read ‘0’

Bit 5..0

R/W

end_fifo: End address of the FIFO

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