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CS89712 データシート(PDF) 96 Page - Cirrus Logic

部品番号 CS89712
部品情報  HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH 10BASE-T ETHERNET CONTROLLER
PDF  170 Pages
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メーカー  CIRRUS [Cirrus Logic]
ホームページ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS89712 データシート(HTML) 96 Page - Cirrus Logic

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CS89712
96
DS502PP2
3.9.2
SDCONF SDRAM Control Register (address 0x8000.2300)
3.9.3
SDRFPR SDRAM Refresh Period Register (address 0x8000.2340)
This 16-bit read/write register sets the interval between SDRAM refresh commands. The value programmed is the
interval in BLCK cycles e.g. for a 16
µs refresh period with a BCLK of 36 MHz, the following value should be used:
16x10-6 * 36x106 = 576
The refresh timer is set to 256 by nPOR to ensure a refresh time of better than 16
µs. This register should not be
programmed to a value below 2 otherwise the internal bus may become locked.
This register replaces DPFPR, which is no longer active. Writes to this register are ignored. Reads from this register
will produce unpredictable results.
0011
04:12
1011
12:04
0100
05:11
1100
13:03
0101
06:10
1101
14:02
0110
07:09
1110
15:01
0111
08:08
1111
16:00 (continually on)
31:11
10
9
8:7
6:5
4:2
1:0
Reserved
SDACTIVE
CLKCTL
SDWIDTH
SDSIZE
Reserved
CASLAT
Bit
Description
1:0.
How many clock cycles after CAS before the device is ready for reading or writing. . . ‘00’ =>
Reserved. . . , ‘01’ => Reserved, ‘10’ => CAS Latency = 2, ‘11’ => CAS Latency = 3. . . . . . . . . . .
The default value is ‘10’ for CAS latency = 2.
4:2.
Reserved.
6:5.
The capacity of each SDRAM. The values are: ‘00’=>16Mits, ‘01’=>64Mbits, ‘10’=>128Mbits,
‘11’=>256Mbits.
8:7.
The width of each SDRAM. ‘00’=>4bits, ‘01’=>8bits, ‘10’=>16 bits, ‘11’=>32 bits.
9.
Control over the SDRAM clock. ‘0’=> SDRAM clock is permanently enabled except when in
standby mode. ‘1’=>SDRAM clock stops when the CS89712 is put into inactive mode i.e.,
SDACTIVE = ‘0’, or when in standby mode.
10.
Enables the SDRAM controller: ‘0’ disables, ‘1’ enables. The SDRAM controller will only initialize
if SDACTIVE is set to 1. After initialization, resetting this parameter will cause the SDRAM con-
troller to enter an inactive state. It will remain in this state until SDACTIVE is set to 1.
31:11.
Reserved.
31:16
15:0
Reserved
REFRATE
LEDFLSH[5:2]
Duty Ratio
(time on: time off)
LEDFLSH[5:2]
Duty Ratio
(time on: time off)
Table 50. LED Duty Ratio (Continued)



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