CS89712 datasheet(5/170 Pages) CIRRUS

5 / 170 page

CS89712

DS502PP2

The CS89712 contains a single-chip embedded

controller designed to be used in low-cost and ul-

tra-low-power applications. Operating at 74 MHz,

the

CS89712

delivers

about

66 Dhrystone

2.1 MIPS sustained (74 MIPS peak).

The CS89712 contains the following features:

•

ARM720T processor with:

ARM7TDMI CPU core (supporting the

Thumb instruction set and with enhanced

multiplier) running at a dynamic clock

speeds of 18, 36, 49, or 74 MHz

Advanced power management

Memory Management Unit compatible

with the ARM710 core (and a 64-entry

translation lookaside buffer) with added

support for Windows CE

8 kbytes of unified instruction/data cache

with a four-way set associative controller

Write buffer

JTAG, core debug and full embedded ICE

•

Full 10BaseT Ethernet port, with all the analog

& digital circuitry needed for a complete Ether-

net circuit, having:

Media Access Control (MAC) IEEE 802.3

compliant full-duplex engine. It handles all

aspects of Ethernet frame transmission and

reception, including: collision detection,

preamble generation and detection, and

CRC generation and test. Features include

automatic retransmission on collision, and

automatic padding of transmitted frames.

4 kbyte page of on-chip memory, eliminat-

ing external memory chips.

serial EEPROM interface allowing config-

uration information storage for automatic

load at power-up.

A Manchester encoder/decoder, clock re-

covery circuit, and 10BASE-T transceiver.

It provides on-chip LED drivers for link sta-

tus, bus status, and Ethernet line activity.

10BASE-T transceiver including drivers,

receivers, and analog filters, for direct con-

nection to low-cost isolation transformers.

very low noise emission, shortening EMI

testing and qualification time.

•

48k bytes of on-chip SRAM sharable between

the LCD controller and general applications

•

Low power operation. Typical power dissipat-

ed is 270 mW at 74 MHz in the Operating State

and 160 mW in the Idle State (clock to the CPU

stopped,

everything

else

running),

with

<150 uW in the Standby State (realtime clock

‘on’, everything else stopped). The Ethernet

block has a Software Suspend state, disabling

the receiver and dropping current to the micro-

ampere range.

•

Advanced audio decoder / decompression sup-

ports multiple audio decompression algorithms

at all standard sample & bit rates. MPEG 1, 2,

and 2.5 layer 3 audio decoding is supported, in-

cluding ISO compliant MPEG 1 and 2 layer 3

support. Adaptive bit rates are supported.

•

Up to 64 MHz of SDRAM can operate at up to

36.864 MHz with 16- or 32-bit wide accesses.

•

ROM / SRAM / FLASH Memory controller de-

codes up to 5 separate memory segments each

up to 256 Mbytes. Each segment can be config-

ured as 8, 16, or 32 bits wide with page-mode

access support and programmable access times.

Supports removable FLASH card interface for

addition of expansion FLASH modules.

•

27 general-purpose I/O bits; three 8-bit and one

3-bit port support scanning keyboard matrix.

•

Digital Audio Interface (DAI) for interfacing to

CD-quality DACs and CODECs.

•

Interrupt controller.

•

IrDA 115.2 kbps SIR protocol controller.

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