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CS89712 データシート(PDF) 155 Page - Cirrus Logic

部品番号 CS89712
部品情報  HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH 10BASE-T ETHERNET CONTROLLER
PDF  170 Pages
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メーカー  CIRRUS [Cirrus Logic]
ホームページ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS89712 データシート(HTML) 155 Page - Cirrus Logic

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CS89712
DS502PP2
155
Figure 27. SDRAM Read Cycles CAS Latency = 2
1. tRCD (delay time ACT to READ/WRITE command) = 30 ns or 2 cycles at 36 MHz.
2. tRP (PRE to ACT command period) = 30 ns or 2 cycles at 36 MHz.
3. tRAS (ACT to PRE command period) = 60 ns or 3 cycles at 36 MHz.
4. tRC (ACT to REF/ACT command period [operation]) = 90 ns or 4 cycles at 36 MHz.
5. For SDCAS latency 3, there will be an extra cycle between T4 and T5.
6. For CAS latency 3, there will be an extra cycle between T4 and T5.
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
nRAS /
nCAS / nWE
NOP
ACT
NOP
T0
READ
NOP
NOP
NOP
NOP
NOP
NOP
(ACT)
CKE
nCS
1 dev
1 dev
DQM
DQ
DI1
Bank sel
A10
(prech sel)
addr
CAS lat 2
tRCD
tRP
tRAS
tRC
auto precharge
row
col
row
bank
bank
NOP
T10
DI2
DI0
DI3



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