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USB2244II-AEZG データシート(PDF) 14 Page - Microchip Technology |
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USB2244II-AEZG データシート(HTML) 14 Page - Microchip Technology |
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14 / 43 page  USB224X DS00001979A-page 14 2010 - 2015 Microchip Technology Inc. xD_nWE 12 O12PU xD Write Enable This pin is an active low write strobe signal for the xD device. When using the internal FET, this pin has a weak internal pull-up resistor that is tied to the output of the internal power FET. If an external FET is used (Internal FET is disabled), then the internal pull-up is not available (external pull-ups must be used). xD_nB/R 17 IPU xD Busy or Data Ready This pin is connected to the BSY/RDY pin of the xD device. When using the internal FET, this pin has a weak internal pull-up resistor that is tied to the output of the internal power FET. If an external FET is used (Internal FET is disabled), then the internal pull-up is not available (external pull-ups must be used). xD_nCD 19 I/O12 xD Card Detection This is designated by the default firmware as the xD- Picture card detection pin. Note: This pin can be left unconnected if the socket is not used. xD_nCE 15 O12PU xD Chip Enable This pin is the active low chip enable signal to the xD device. When using the internal FET, this pin has a weak internal pull-up resistor that is tied to the output of the internal power FET. If an external FET is used (Internal FET is disabled), then the internal pull-up is not available (external pull-ups must be used). MEMORY STICK (MS) INTERFACE MS_D[7:0] 8 7 4 5 23 20 10 11 I/O12PD MS System Data In/Out These pins are the bi-directional data signals for the MS device. MS_D0, MS_D2, and MS_D3 have weak pull- down resistors. In serial mode, the most significant bit (MSB) of each byte is transmitted first by either MSC or MS device on MS_D0. In parallel mode, MS_D1 has a pull-down resistor, otherwise it is disabled. In 4- or 8-bit parallel mode, there is a weak pull-down resistor on all MS_D7 - 0 signals. TABLE 6-1: USB224X 36-PIN QFN PIN DESCRIPTIONS (CONTINUED) Symbol Buffer Type Description |
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