MB91F577CSPMC datasheet(115/163 Pages) CYPRESS

部品番号	MB91F577CSPMC

部品情報	32-bit RISC, load/store architecture, 5-stage pipeline

PDF	163 Pages

Scroll/Zoom	100%

メーカー	CYPRESS [Cypress Semiconductor]

ホームページ	http://www.cypress.com

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115 / 163 page

Document Number: 002-04725 Rev.*A

Page 115 of 163

MB91570 Series

13.4 AC Characteristics

13.4.1

Main Clock Timing

(TA: Recommended operating conditions, VCC5 = 5.0V±10%, VSS = DVSS = AVSS = 0.0V)

Parameter

Symbol

name

Conditio

Value

Unit

Remarks

Min

Typ

Max

Source oscillation clock

frequency

X0,X1

–

MHz

Source oscillation clock cycle

time

tCYL

X0,X1

–

250

–

Internal operating clock cycle

time*

FCP

–

MHz

CPU clock

FCPP

–

MHz

Peripheral bus clock

FCPT

–

MHz

External bus clock

Internal operating clock cycle

time*

tCP

–

12.5

–

500

CPU clock

tCPP

–

500

Peripheral bus clock

tCPT

–

500

External bus clock

CAN PLL jitter

(when lock)

tPJ

–

-10

–

+10

FCP = 80MHz (4MHz×Multiplied by

20)

Built-in CR oscillation frequency FCCR

–

100

200

kHz

*: The maximum / minimum value is defined when using the main clock and PLL clock.

X0,X1 clock timing

CAN PLL jitter

Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles.

tCYL

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