TNETV1644ZDU6 datasheet(225/306 Pages) TI1

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6.10.2.2 Video Encoder (VENC)

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

Table 6-40. OSD Register Descriptions (continued)

0x01C7 26EC

CLUTRAMYCB

CLUT RAMYCB Setup

0x01C7 26F0

CLUTRAMCR

CLUT RAM Setup

0x01C7 26F4

TRANSPVAL

CLUT RAM Setup

0x01C7 26F8

RSV6

Reserved

0x01C7 26FC

PPVWIN0ADR

Ping-Pong Video Window 0 Address

Analog/DACs interface of the Video Encoder (VENC) supports the following features.

• Master Clock Input - 27MHz (x2 Upsampling)

• SDTV Support

–

Composite NTSC-M, PAL-B/D/G/H/I

–

S-Video (Y/C)

–

Component YPbPr (SMPTE/EBU N10, Betacam, MII)

–

RGB

–

Non-Interlace

–

CGMS/WSS

–

Line 21 Closed Caption Data Encoding

–

Chroma Low Pass Filter 1.5MHz/3MHz

–

Programmable SC-H phase

• HDTV Support

–

Progressive Output (525p/625p)

–

Component YPbPr

–

RGB

–

CGMS/WSS

• 4 10-bit Over-Sampling D/A Converters

• Optional 7.5% Pedestal

• 16-235/0-255 Input Amplitude Selectable

• Programmable Luma Delay

• Master/Slave Operation

• Internal Color Bar Generation (100%/75%)

The Digital LCD Controller (DLCD) of the VENC supports the following features.

• Programmable DCLK

• Various Output Formats

–

YCbCr 16bit

–

YCbCr 8bit

–

ITU-R BT. 656

–

Parallel RGB 24bit

• Low Pass Filter for Digital RGB Output

• Programmable Timing Generator

• Master/Slave Operation

• Internal Color Bar Generation (100%/75%)

The VENC register memory mapping including the Digital LCD and DACs is shown in Table 6-41.

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