TNETV1644ZDU6 datasheet(109/306 Pages) TI1

109 / 306 page

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

Table 3-20. PINMUX1 Register Descriptions (continued)

Bit

Field Name

Description

Pins Controlled

Reserved. For proper device operation, the user should only write "0" to this bit

RSV

–

(default).

Host Block:

VLYNQ_CLOCK/PCICLK/GP[57]

Host Block Pin Select.

HD0/VLYNQ_SCRUN/AD18/GP[58]

If EMAC opertaion is desired, EMAC must be placed in reset before

HD1/VLYNQ_RXD0/AD16/GP[59]

programminng PINMUX1 HOSTBK to select EMAC pins.

HD2/VLYNQ_RXD1/AD17/GP[60]

HD3/VLYNQ_RXD2/PCBE2/GP[61]

PCIEN = 0 and HOSTBK = 000: GPIO Mode (default if PCIEN = 0).

HD4/VLYNQ_RXD3/PFRAME/GP[62]

Pins function as GPIO (GP[83:57]).

HD5/VLYNQ_TXD0/PIRDY/GP[63]

HD6/VLYNQ_TXD1/PTRDY/GP[64]

PCIEN = 0 and HOSTBK = 001: HPI + 1 GPIO Mode.

HD7/VLYNQ_TXD2/PDEVSEL/GP[65]

Pins function as HPI and GPIO (GP[57]).

HD8/VLYNQ_TXD3/PPERR/GP[66]

PCIEN = 0 and HOSTBK = 010: VLYNQ + 17 GPIO Mode.

HD9/MCOL/PSTOP/GP[67]

Pins function as VLYNQ (VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0],

HD10/MCRS/PSERR/GP[68]

VLYNQ_TXD[3:0]), and GP[83:67].

HD11/MTXD3/PCBE1/GP[69]

HD12/MTXD2/PPAR/GP[70]

PCIEN = 0 and HOSTBK = 011: VLYNQ + MII + MDIO Mode.

6:4

HOSTBK

HD13/MTXD1/AD14/GP[71]

Pins function as VLYNQ (VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0],

HD14/MTXD0/AD15/GP[72]

VLYNQ_TXD[3:0]), MII (TXCLK, CRS, COL, TXD[3:0], RXVD, TXEN, RXER,

HD15/MTXCLK/AD12/GP[73]

RXCLK, RXD[3:0]), and MDIO (MDIO, MDC).

HHWIL/MRXDV/AD13/GP[74]

HCNTL1/MTXEN/AD11/GP[75]

PCIEN = 0 and HOSTBK = 100: MII + MDIO +10 GPIO Mode.

HCNTL0/MRXER/AD10/GP[76]

Pins function as MII (TXCLK, CRS, COL, TXD[3:0], RXVD, TXEN, RXER,

HR/W/MRXCLK/AD8/GP[77]

RXCLK, RXD[3:0]), MDIO (MDIO, MDC), and GP[66:57].

HDS2/MRXD0/AD9/GP[78]

HDS1/MRXD1/AD7/GP[79]

PCIEN = 1 and HOSTBK = 000: PCI Mode (default if PCIEN = 1).

HRDY/MRXD2/PCBE0/GP[80]

Pins function as PCI pins: PCICLK, PCBE2, PCBE1, PCBE0, PFRAME,

HCS/MDCLK/AD5/GP[81]

PIDRDY, PTRDY, PDEVSEL, PPER, PSTOP, PSERR, PPAR, AD[18:5], and

HINT/MRXD3/AD6/GP[82]

AD03.

HAS/MDIO/AD3/GP[83]

All other PCIEN and HOSTBK combinations reserved.

The combination of PINMUX1 fields PCIEN and

HOSTBK select the function of these 27 pins.

Reserved. For proper device operation, the user should only write "0" to this bit

3:1

RESERVED

–

(default).

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