ST7LITE49K2 datasheet(133/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

On-chip peripherals

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10: Timer clock = fCPU/8

11: Timer clock = external clock (where available)

Note:

If the external clock pin is not available, programming the external clock configuration stops

the counter.

Bit 1 = IEDG2 Input edge 2

This bit determines which type of level transition on the ICAP2 pin triggers the capture.

0: A falling edge triggers the capture

1: A rising edge triggers the capture

Bit 0 = EXEDG External clock edge

This bit determines which type of level transition on the external clock pin EXTCLK

triggers the counter register.

0: A falling edge triggers the counter register

1: A rising edge triggers the counter register

Timer A control/status register (TACSR)

Reset value: 0000 0000 (00h)

The 3 least significant bits are not used.

Bit 7 = ICF1 Input capture flag 1

0: No input capture (reset value)

1: An input capture has occurred on the ICAP1 pin or the counter has reached the

OC2R value in PWM mode. To clear this bit, first read the SR register, then read or

write the low byte of the IC1R (IC1LR) register.

Bit 6 = OCF1 Output compare flag 1

0: No match (reset value)

1: The content of the free running counter has matched the content of the OC1R

the OC1R (OC1LR) register.

Bit 5 = TOF Timer overflow flag

0: No timer overflow (reset value)

1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first

read the SR register, then read or write the low byte of the CR (CLR) register.

Note:

Reading or writing the ACLR register does not clear TOF.

ICF1

OCF1

TOF

ICF2

OCF2

TIMD

Reserved

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