AD9681_17 datasheet(32/41 Pages) AD

32 / 41 page

Data Sheet

AD9681

Rev. C | Page 31 of 40

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations.

The memory map is divided into three sections: the chip confi-

guration registers (Address 0x00 to Address 0x02); the device

index and transfer registers (Address 0x05 and Address 0xFF);

and the global ADC function registers, including setup, control,

and test (Address 0x08 to Address 0x109).

The memory map register table (see Table 17) lists the default

hexadecimal value for each hexadecimal address shown. The

column with the Bit 7 (MSB) heading is the start of the default

hexadecimal value given. For example, Address 0x05, the device

index register, has a hexadecimal default value of 0x3F. This means

that in Address 0x05, Bits[7:6] = 0, and the remaining bits,

Bits[5:0], = 1. This setting is the default channel index setting.

The default value results in all specified ADC channels receiving

the next write command. For more information on this function

and others, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI. This application note details the

functions controlled by Register 0x00 to Register 0xFF. The

remaining registers are documented in the Memory Map

Open Locations

All address and bit locations that are not listed in Table 17 are

not currently supported for this device. Write the unused bits of

a valid address location with 0s. Writing to these locations is

required only when some of the bits of an address location are

valid (for example, Address 0x05). Do not write to an address

location if the entire address location is open or if the address is

not listed in Table 17 (for example, Address 0x13).

Default Values

After the AD9681 is reset (via Bit 5 and Bit 2 of Address 0x00),

the registers are loaded with default values. The default values

for the registers are listed in the Default Value (Hex) column

of Table 17, the memory map register table.

Logic Levels

An explanation of logic level terminology follows:



“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”



“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Channel Specific Registers

Some channel setup functions can be programmed independently

for each channel. In such cases, channel address locations are

internally duplicated for each channel; that is, each channel has

its own set of registers. These registers and bits are designated in

Table 17 as local. Access these local registers and bits by setting

the appropriate data channel bits (A1, A2 through D1, D2) and

the clock channel bits (DCO±1, DCO±2 and FCO±1, FCO±2),

found in Register 0x05. If all the valid bits are set in Register

0x05, the subsequent write to a local register affects the registers

of all the data channels and the DCO±x/FCO±x clock channels.

In a read cycle, set only one channel (A1, A2 through D1, D2)

to read one local register. If all the bits are set during a SPI read

cycle, the device returns the value for Channel A1.

Registers and bits that are designated as global in Table 17 are

applicable to the channel features for which independent settings

are not allowed; thus, they affect the entire device. The settings

in Register 0x05 do not affect the global registers and bits.

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