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AD9681

Data Sheet

Rev. C | Page 20 of 40

THEORY OF OPERATION

The AD9681 is a multistage, pipelined ADC. Each stage

provides sufficient overlap to correct for flash errors in the

preceding stage. The quantized outputs from each stage are

combined into a final 14-bit result in the digital correction

logic. The serializer transmits this converted data in a 16-bit

output. The pipelined architecture permits the first stage to

operate with a new input sample while the remaining stages

operate with preceding samples. Sampling occurs on the rising

edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor DAC

and an interstage residue amplifier (for example, a multiplying

digital-to-analog converter (MDAC)). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

The output staging block aligns the data, corrects errors, and

passes the data to the output buffers. The data is then serialized

and aligned to the frame and data clocks.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9681 is a differential switched

capacitor circuit designed for processing differential input signals.

This circuit can support a wide common-mode range while

maintaining excellent performance. By using an input common-

mode voltage of midsupply, users can minimize signal dependent

errors and achieve optimum performance.

CPAR

CSAMPLE

CPAR

VIN–x1,

VIN–x2

VIN+x1,

VIN+x2

Figure 35. Switched Capacitor Input Circuit

The clock signal alternately switches the input circuit between

sample mode and hold mode (see Figure 35). When the input

circuit is switched to sample mode, the signal source must be

capable of charging the sample capacitors and settling within

one-half of a clock cycle. A small resistor, in series with each

input, can help reduce the peak transient current injected from

the output stage of the driving source. In addition, low Q inductors

or ferrite beads can be placed on each leg of the input to reduce

high differential capacitance at the analog inputs and, therefore,

achieve the maximum bandwidth of the ADC. Such use of low

Q inductors or ferrite beads is required when driving the converter

front end at high IF frequencies. Place either a differential capacitor

or two single-ended capacitors on the inputs to provide a matching

passive network. This configuration ultimately creates a low-pass

filter at the input to limit unwanted broadband noise. See the

AN-742 Application Note, Frequency Domain Response of

Switched-Capacitor ADCs; the AN-827 Application Note, A

Resonant Approach to Interfacing Amplifiers to Switched-

Capacitor ADCs; and the Analog Dialogue article “Transformer-

Coupled Front-End for Wideband A/D Converters” (Volume 39,

April 2005) for more information. In general, the precise values

vary, depending on the application.

Input Common Mode

The analog inputs of the AD9681 are not internally dc biased.

Therefore, in ac-coupled applications, the user must provide

this bias externally. For optimum performance, set the device so

that VCM = AVDD/2. However, the device can function over a

wider range with reasonable performance, as shown in Figure 36.

An on-chip, common-mode voltage reference is included in the

design and is available at the VCMx pin. Decouple the VCMx pin

to ground using a 0.1 μF capacitor, as described in the Applications

Information section.

Maximum SNR performance is achieved by setting the ADC to

the largest span in a differential configuration. In the case of the

AD9681, the largest available input span is 2 V p-p.

100

0.5

VCM (V)

0.7

0.9

1.1

1.3

SNR (dBFS)

SFDR (dBc)

Figure 36. SNR/SFDR vs. Common-Mode Voltage;

fIN = 9.7 MHz, fSAMPLE = 125 MSPS

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