AD9230-11 datasheet(6/29 Pages) AD

6 / 29 page

AD9230-11

Rev. 0 | Page 5 of 28

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

Table 3.

Parameter1

Temp

Min

Typ

Max

Unit

CLOCK INPUTS

Logic Compliance

Full

CMOS/LVDS/LVPECL

Internal Common-Mode Bias

Full

1.2

Differential Input Voltage

Full

0.2

V p-p

Input Voltage Range

Full

AGND − 0.3

AVDD + 1.6

Input Common-Mode Range

Full

1.1

AVDD

High Level Input Voltage (VIH)

Full

1.2

3.6

Low Level Input Voltage (VIL)

Full

0.8

High Level Input Current (IIH)

Full

−10

+10

μA

Low Level Input Current (IIL)

Full

−10

+10

μA

Input Resistance (Differential)

Full

kΩ

Input Capacitance

Full

LOGIC INPUTS

Logic 1 Voltage

Full

0.8 × AVDD

Logic 0 Voltage

Full

0.2 × AVDD

Logic 1 Input Current (SDIO)

Full

μA

Logic 0 Input Current (SDIO)

Full

−60

μA

Logic 1 Input Current (SCLK, PWDN, CSB, RESET)

Full

μA

Logic 0 Input Current (SCLK, PWDN, CSB, RESET)

Full

μA

Input Capacitance

25°C

LOGIC OUTPUTS2

VOD Differential Output Voltage

Full

247

454

VOS Output Offset Voltage

Full

1.125

1.375

Output Coding

Twos complement, gray code, or offset binary (default)

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were

completed.

2 LVDS RTERMINATION = 100 Ω.

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