Data Sheet

AD9252

Rev. E | Page 3 of 52

SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 1.

AD9252-50

Parameter1

Temperature

Min

Typ

Max

Unit

RESOLUTION

14

Bits

ACCURACY

No Missing Codes

Full

Guaranteed

Offset Error

Full

±1

±8

mV

Offset Matching

Full

±3

±8

mV

Gain Error

Full

±1.5

±2.5

% FS

Gain Matching

Full

±0.3

±0.7

% FS

Differential Nonlinearity (DNL)

Full

±0.4

±1

LSB

Integral Nonlinearity (INL)

Full

±1.5

±4

LSB

TEMPERATURE DRIFT

Offset Error

Full

±2

ppm/°C

Gain Error

Full

±17

ppm/°C

Reference Voltage (1 V Mode)

Full

±21

ppm/°C

REFERENCE

Output Voltage Error (VREF = 1 V)

Full

±2

±30

mV

Load Regulation @ 1.0 mA (VREF = 1 V)

Full

3

mV

Input Resistance

Full

6

kΩ

ANALOG INPUTS

Differential Input Voltage Range (VREF = 1 V)

Full

2

V p-p

Common-Mode Voltage

Full

AVDD/2

V

Differential Input Capacitance

Full

7

pF

Analog Bandwidth, Full Power

Full

325

MHz

POWER SUPPLY

AVDD

Full

1.7

1.8

1.9

V

DRVDD

Full

1.7

1.8

1.9

V

IAVDD

Full

360

373.4

mA

IDRVDD

Full

55.5

58

mA

Total Power Dissipation (Including Output Drivers)

Full

748

773

mW

Power-Down Dissipation

Full

2

11

mW

Standby Dissipation2

Full

89

mW

CROSSTALK

AIN = −0.5 dBFS

Full

−90

dB

Overrange3

Full

−90

dB

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

Can be controlled via the SPI.

3

Overrange condition is specific with 6 dB of the full-scale input range.