AD9252

Data Sheet

Rev. E | Page 6 of 52

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 4.

AD9252-50

Parameter1

Temp

Min

Typ

Max

Unit

CLOCK2

Maximum Clock Rate

Full

50

MSPS

Minimum Clock Rate

Full

10

MSPS

Full

10.0

ns

Full

10.0

ns

OUTPUT PARAMETERS2, 3

Full

1.5

2.3

3.1

ns

Full

300

ps

Full

300

ps

Full

1.5

2.3

3.1

ns

Full

ns

Full

ps

Full

ps

Full

±50

±200

ps

Wake-Up Time (Standby)

25°C

600

ns

Wake-Up Time (Power-Down)

25°C

375

μs

Pipeline Latency

Full

8

CLK cycles

APERTURE

25°C

750

ps

Aperture Uncertainty (Jitter)

25°C

<1

ps rms

Out-of-Range Recovery Time

25°C

1

CLK cycles

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

Can be adjusted via the SPI.

3

Measurements were made using a part soldered to FR-4 material.

4