CS62180 datasheet(13/50 Pages) CIRRUS

13 / 50 page

ment will be moved forward by the least number

of bits necessary to be in alignment with the new

frame boundary.

Figure 5 shows the bit-level timing (with signal-

ling enabled). Note that the delay from input to

output is 10 TCLK cycles. TCHCLK transitions

high at the beginning of every DS0 channel

(50% duty cycle).

193S Timing

Frame and multiframe timing is output on

TCHCLK, TMO, TSIGSEL, TSIGFR, and

TLCLK. TMO transitions high at the beginning

of every superframe (50% duty cycle). TSIGFR

goes high during signaling frames (every 6

frames). TLCLK is a 4 kHz clock for the TLINK

input. TLCLK goes high during odd frames (ex-

ternal S-bit insertion).

TSIGSEL runs at twice the frequency of TMO.

Logical combination of TMO and TSIGSEL pro-

vides a way to distinguish the 6

th and 12th

frames for external multiplexing of signaling

channels. TMO is high for channel A, and low

for B. See Figure 6 for timing diagram.

193E Timing

Frame and multiframe timing is output on

TCHCLK, TMO, TSIGSEL, TSIGFR, and

TLCLK. TMO transitions high at the beginning

of every superframe (50% duty cycle). TSIGFR

goes high during signaling frames (every 6

frames). TLCLK is a 4 kHz clock for the TLINK

input. TLCLK goes high during odd frames

(FDL insertion).

TSIGSEL runs at twice the frequency of TMO.

Logical combination of TMO and TSIGSEL pro-

vides a way to distinguish the 6th, 12th, 18th,

and 24th frames for external multiplexing of sig-

naling channels.

TMO is high for channels A

and B, and TSIGSEL is high for channels A and

C. See Figure 7 for timing diagram.

TCLK

TMSYNC

TFSYNC

TLINK

TSIGFR

TABCD

TSER

TCHCLK

10 TCLK Cycle Delay

TMO,

TSIGSEL,

TLCLK

TPOS,

TNEG

D23

D24 F1

D24

D23

Figure 5. Bit Level Transmit Timing (193E, signaling enabled)

CS62180B

DS225PP2

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