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ATSAMB11XR データシート(PDF) 29 Page - Microchip Technology |
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ATSAMB11XR データシート(HTML) 29 Page - Microchip Technology |
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29 / 87 page  0x12 RESERVED 0x13 QUAD DECODER 0x14 RESERVED 0x15 RESERVED 0x16 RESERVED 0x17 RESERVED 0x18 BROWNOUT DETECTED 7.1.3.11 GPIO Controller The AHB GPIO is a general-purpose I/O interface unit that allows the CPU to independently control all input or output signals on the ATSAMB11-XR2100A and ATSAMB11-ZR210CA. These can be used for a wide variety of functions pertaining to the application. The AHB GPIO provides a 16-bit I/O interface with the following features: • Programmable interrupt generation capability • Programmable masking support • Thread-safe operation by providing separate set and clear addresses for control registers • Inputs are sampled using a double flip-flop to avoid meta-stability issues 7.2 Memory Subsystem The Cortex-M0 core uses a 128 KB instruction/boot ROM along with a 128 KB shared instruction and data RAM. Refer to BluSDK SMART BLE API Software Development Guide for the memory map of this memory section. 7.2.1 Shared Instruction and Data Memory The Instruction and Data Memory (IDRAM1 and IDRAM2) contains instructions and data used by the ARM. The 128 KB size of IDRAM1 and IDRAM2 is used for BLE subsystem and also for the user application. IDRAM1 contains three 32 KB memories and IDRAM2 contains two 16 KB memories that are accessible to the ARM and used for instruction/data storage. 7.2.2 ROM The ROM is used to store the boot code and BLE firmware, stack, and selected user profiles. The ROM contains the 128 KB memory that is accessible to the ARM. The Boot loader code stored in ROM loads the application from Flash to RAM. 7.2.3 BLE Retention Memory The BLE functionality requires 8 KB state, instruction, and data to be retained in memory, when the processor either goes into Sleep mode or Power down mode. The RAM is separated into specific power domains to allow tradeoff in power consumption with retention memory size. 7.3 Non-Volatile Memory The ATSAMB11-XR2100A and ATSAMB11-ZR210CA have 768 bits of non-volatile eFuse memory that can be read by the CPU after device reset. This memory region is one-time- programmable. It is ATSAMB11XR/ZR © 2017 Microchip Technology Inc. Datasheet Preliminary DS70005342A-page 29 |
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