AD9520-1SLASHPCBZ datasheet(39/80 Pages) AD

39 / 80 page

Data Sheet

AD9520-1

Rev. B | Page 39 of 80

External VCXO/VCO Clock Input (CLK/CLK)

This differential input is used to drive the AD9520-1 clock

distribution section. This input can receive up to 2.4 GHz.

The pins are internally self-biased, and the input signal should

be ac-coupled via capacitors.

CLOCK INPUT

STAGE

CLK

5kΩ

2.5kΩ

Figure 46. CLK Equivalent Input Circuit

The CLK/CLK input can be used either as a distribution only

input (with the PLL off) or as a feedback input for an external

VCO/VCXO using the internal PLL when the internal VCO is

not used. These inputs are also used as a feedback path for the

external zero delay mode.

Holdover Mode

The AD9520-1 PLL has a holdover function. Holdover mode

allows the VCO to maintain a relatively constant frequency even

though there is no reference clock. This function is useful when

the PLL reference clock is lost. Holdover is implemented by

placing the charge pump in a high impedance state. Without

this function, the charge pump is placed into a constant pump-up

or pump-down state, resulting in a massive VCO frequency

shift. Because the charge pump is placed in a high impedance

state, any leakage that occurs at the charge pump output or the

VCO tuning node causes a drift of the VCO frequency. This

drift can be mitigated by using a loop filter that contains a large

capacitive component because this drift is limited by the current

leakage-induced slew rate (ILEAK/C) of the VCO control voltage.

Both a manual holdover mode, using the SYNC pin, and an

automatic holdover mode are provided. To use either function, the

holdover function must be enabled (Register 0x01D[0]).

Manual/External Holdover Mode

A manual holdover mode can be enabled that allows the user to

place the charge pump into a high impedance state when the

SYNC pin is asserted low. This operation is edge sensitive, not

level sensitive. The charge pump enters a high impedance state

immediately. To take the charge pump out of a high impedance

state, take the SYNC pin high. The charge pump then leaves the

high impedance state synchronously with the next PFD rising

edge from the reference clock. This prevents extraneous charge

pump events from occurring during the time between SYNC

going high and the next PFD event. This also means that the

charge pump stays in a high impedance state if no reference

clock is present.

The B counter (in the N divider) is reset synchronously with the

charge pump, leaving the high impedance state on the reference

path PFD event. This helps align the edges out of the R and N

dividers for faster settling of the PLL. Because the prescaler is

not reset, this feature works best when the B and R numbers are

close, resulting in a smaller phase difference for the loop to

settle out.

When using this mode, set the channel dividers to ignore the

SYNC pin (at least after an initial SYNC event). If the dividers are

not set to ignore the SYNC pin, the distribution outputs turn off

when SYNC is taken low to put the part into holdover mode. The

channel divider ignore SYNC function is programmed in Bit 6 of

for Channel Divider 0, Channel Divider 1, Channel Divider 2, and

Channel Divider 3, respectively.

Automatic/Internal Holdover Mode

When enabled, this function automatically places the charge

pump into a high impedance state when the loop loses lock.

The assumption is that the only reason the loop loses lock is due

to the PLL losing the reference clock; therefore, the holdover

function puts the charge pump into a high impedance state to

maintain the VCO frequency as close as possible to the original

frequency before the reference clock disappeared.

The holdover function senses the logic level of the LD pin as a

condition to enter holdover. The signal at LD can be from the DLD,

ALD, or current source LD mode. The LD comparator can be

disabled (Register 0x01D[3]), which causes the holdover function

to always sense LD as being high. If DLD is used, it is possible

for the DLD signal to chatter while the PLL is reacquiring lock.

The holdover function may retrigger, thereby preventing the

holdover mode from terminating. Use of the current source lock

detect mode is recommended to avoid this situation (see the

Current Source Digital Lock Detect (CSDLD) section).

When in holdover mode, the charge pump stays in a high

impedance state as long as there is no reference clock present.

As in the external holdover mode, the B counter (in the N divider)

is reset synchronously with the charge pump leaving the high

impedance state on the reference path PFD event. This helps

align the edges out of the R and N dividers for faster settling of

the PLL and reduces frequency errors during settling. Because

the prescaler is not reset, this feature works best when the B and

R numbers are close because this results in a smaller phase

difference for the loop to settle out.

After leaving holdover, the loop then reacquires lock, and the

LD pin must go high (if Register 0x01D[3] = 1b) before it can

reenter holdover (CP high impedance).

The holdover function always responds to the state of the

currently selected reference (Register 0x01C). If the loop loses

lock during a reference switchover (see the Reference Switchover

section), holdover is triggered briefly until the next reference clock

edge at the PFD.

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