データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

AD9520-1/PCBZ データシート(PDF) 13 Page - Analog Devices

部品番号 AD9520-1/PCBZ
部品情報  12 LVPECL/24 CMOS Output Clock Generator
PDF  80 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9520-1/PCBZ データシート(HTML) 13 Page - Analog Devices

Back Button AD9520-1/PCBZ Datasheet HTML 9Page - Analog Devices AD9520-1/PCBZ Datasheet HTML 10Page - Analog Devices AD9520-1/PCBZ Datasheet HTML 11Page - Analog Devices AD9520-1/PCBZ Datasheet HTML 12Page - Analog Devices AD9520-1/PCBZ Datasheet HTML 13Page - Analog Devices AD9520-1/PCBZ Datasheet HTML 14Page - Analog Devices AD9520-1/PCBZ Datasheet HTML 15Page - Analog Devices AD9520-1/PCBZ Datasheet HTML 16Page - Analog Devices AD9520-1/PCBZ Datasheet HTML 17Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 80 page
background image
Data Sheet
AD9520-1
Rev. B | Page 13 of 80
SERIAL CONTROL PORT—SPI MODE
Table 13.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CS (INPUT)
CS has an internal 30 kΩ pull-up resistor
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
3
µA
Input Logic 0 Current
−110
µA
The minus sign indicates that current is flowing
out of the AD9520-1, which is due to the
internal pull-up resistor
Input Capacitance
2
pF
SCLK (INPUT IN SPI MODE)
SCLK has an internal 30 kΩ pull-down resistor in
SPI mode but not in I2C mode
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
110
µA
Input Logic 0 Current
1
µA
Input Capacitance
2
pF
SDIO (INPUT IN BIDIRECTIONAL MODE)
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
1
µA
Input Logic 0 Current
1
µA
Input Capacitance
2
pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
2.7
V
Output Logic 0 Voltage
0.4
V
TIMING
Clock Rate (SCLK, 1/tSCLK)
25
MHz
Pulse Width High, tHIGH
16
ns
Pulse Width Low, tLOW
16
ns
SDIO to SCLK Setup, tDS
4
ns
SCLK to SDIO Hold, tDH
0
ns
SCLK to Valid SDIO and SDO, tDV
11
ns
CS to SCLK Setup and Hold, tS, tC
2
ns
CS Minimum Pulse Width High, tPWH
3
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com