AD9520-1SLASHPCBZ datasheet(49/80 Pages) AD

49 / 80 page

Data Sheet

AD9520-1

Rev. B | Page 49 of 80

LVPECL Output Drivers

The LVPECL differential voltage (VOD) is selectable (from

~400 mV to 960 mV, see Bit 1 and Bit 2 in Register 0x0F0 to

power supply (VS_DRV), allowing a separate power supply to

be used. VS_DRV can be set to either 2.5 V or 3.3 V.

The LVPECL output polarity can be set as noninverting or

inverting, which allows for the adjustment of the relative

polarity of outputs within an application without requiring a

board layout change. Each LVPECL output can be powered

down or powered up as needed. Because of the architecture of

the LVPECL output stages, there is the possibility of electrical

overstress and breakdown under certain power-down conditions.

For this reason, the LVPECL outputs have two power-down

modes: total power-down and safe power-down.

200Ω

SW1B

SW1A

SW2

QN2

QN1

OUT

4.4mA

Figure 54. LVPECL Output Simplified Equivalent Circuit

In total power-down mode, all output drivers are shut off

simultaneously. This mode must not be used if there is an

external voltage bias network (such as Thevenin equivalent

termination) on the output pins that causes a dc voltage to

appear at the powered down outputs. However, total power-

down mode is allowed when the LVPECL drivers are terminated

using only pull-down resistors. The total power-down mode is

activated by setting Register 0x230[1].

The primary power-down mode is the safe power-down mode.

This mode continues to protect the output devices while

powered down. There are three ways to activate safe power-

down mode: individually set the power-down bit for each

driver, power down an individual output channel (all of the

drivers associated with that channel are powered down

automatically), and activate sleep mode.

CMOS Output Drivers

The user can also individually configure each LVPECL output as a

pair of CMOS outputs, which provides up to 24 CMOS outputs.

When an output is configured as CMOS, CMOS Output A and

CMOS Output B are automatically turned on. For any given

differential pair, either CMOS Output A or CMOS Output B

can be turned on or off independently.

The user can also select the relative polarity of the CMOS outputs

for any combination of inverting and noninverting (refer to

OUT1/

OUT1

VS_DRV

Figure 55. CMOS Equivalent Output Circuit

Each CMOS output can be powered down, as needed, to save

power. The CMOS output power-down is individually controlled

by the enable CMOS output bits, Bits[6:5] in Register 0x0F0 to

powered down.

Note that activating a CMOS driver in the same output channel

group as the LVPECL drivers may cause the LVPECL driver

performance to degrade. In applications where jitter performance

is critical, the user should test the desired configuration using

an evaluation board, and special steps may need to be taken to

ensure the desired performance.

RESET MODES

The AD9520-1 has a power-on reset (POR) and several other

ways to apply a reset condition to the chip.

Power-On Reset

During chip power-up, a power-on reset pulse is issued when VS

reaches ~2.6 V (<2.8 V) and restores the chip either to the setting

that is stored in the EEPROM (with the EEPROM pin = 1b) or

to the on-chip setting (with the EEPROM pin = 0b). At power-on,

the AD9520-1 also executes a SYNC operation approximately 50

ms after the supply reaches ~2.4 V, which brings the outputs

into phase alignment according to the default settings. It takes

~70 ms for the outputs to begin toggling after the power-on

reset pulse signal is internally generated.

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